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DesignCon 2019 Presentation Viewer
Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.
Tuesday | 8:00 am
Location: Mission City Ballroom Foyer
Track: Welcome Breakfast
Session Type: Networking
Tuesday | 9:00 am
Boot Camp – Machine Learning & Artificial Intelligence for Hardware & Electronics Design
Speakers: Christopher Cheng (Hewlett Packard Enterprise), Paul Franzon (North Carolina State University), Madhavan Swaminathan (Georgia Institute of Technology), YongJin Choi (HP Enterprise), Ting Zhu (HP Enterprise), Seamus Brokaw (Tektronix), Majid Ahadi Dolatsara (Georgia Institute of Technology, Atlanta), Huan Yu (Georgia Institute of Technology), Hakki Mert Torun (Georgia Institute of Technology)
Location: Great America 2
Track: 15. Machine Learning for Microelectronics, Signaling & System Design
Session Type: Boot Camp
Boot Camp – Power Integrity Hands-On Simulation & Measurement
Speakers: Heidi Barnes (Keysight Technologies), Steve Sandler (Picotest.com), Jack Carrel (Xilinx), JackJack Carrel (Xilinx)
Location: Ballroom E
Track: 11. Power Integrity in Power Distribution Networks
Session Type: Boot Camp
Boot Camp – The Art of Signal Integrity Analysis
Speakers: Davi Correia (Carlisle IT), Jason Elllson (Amphenol), David Banas (Haskware)
Location: Ballroom G
Track: 14. Modeling & Analysis of Interconnects
Session Type: Boot Camp
Speakers: Steve Sekel (Keysight Technologies), Richard Mellitz (Samtec), Robert Schaefer (Keysight), Mike Resso (Keysight Technologies), Edward Sayre (Samtec)
Location: Ballroom C
Track: 13. Applying Test & Measurement Methodology, 08. Optimizing High-Speed Serial Design
Session Type: Tutorial
Tutorial – Advanced IBIS-AMI Techniques for 32 GT/s & Beyond
Speakers: Greg Edlund (IBM), Kumar Keshavan (Cadence Design Systems, Inc.), Mehdi Mechaik (Cadence Design Systems, Inc.), Ambrish Varma (Cadence Design Systems), Ken Willis (Cadence Design Systems)
Location: Ballroom A
Track: 02. Chip I/O & Functional Block Modeling & Validation Solutions, 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors
Session Type: Tutorial
Tutorial – Lowering the Barrier to Entry for Electronic/Photonic ICs
Speakers: James Pond (Lumerical), Gilles Lamant (Cadence Design Systems), Samir Chaudhry (TowerJazz), Ahmadreza Farsaei (Cadence), Kerry Schutz (Mathworks)
Location: Ballroom B
Track: 03. Integrating Photonics & Wireless in Electrical Design
Session Type: Tutorial
Tutorial – Recent Advances in Extracting DK, DF & Roughness of PCB Material
Speakers: Jayaprakash Balachandran (Cisco), Kevin Cai (Cisco), Anna Gao (Cisco), Bidyut Sen (Cisco), Pin Jen Wang (Hirose Electric), Jeremy Buan (Hirose Electric), Ching-Chao Huang (Ataitec), Clement Luk (Samtec)
Location: Ballroom D
Track: 05. Advances in Materials & Processing for PCBs, Modules & Packages
Session Type: Tutorial
Tuesday | 12:00 pm
Keynote – Quantum Computing: Future Challenges for Testing & Commercial Implementation
Keynote: Irfan Siddiqi (University of California, Berkeley)
Location: Elizabeth A. Hangs Theater
Track: Keynote
Session Type: Keynote (Free)
Tuesday | 1:30 pm
Speaker: Mike Li (Intel)
Location: Ballroom D
Track: 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors
Session Type: Tutorial
Tutorial – Design With Confidence Using 16Gb/s GDDR6 Memory
Speakers: Tim Hollis (Micron), Michael Richter (Micron), Christopher Kuhn (Micron), Shu Wang (Cadence), Marc Greenberg (Cadence)
Location: Ballroom B
Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques
Session Type: Tutorial
Tutorial – How to Design Good PDN Filters
Speaker: Istvan Novak (Samtec)
Location: Ballroom C
Track: 11. Power Integrity in Power Distribution Networks
Session Type: Tutorial
Tutorial – Radiated Emissions: Debugging & Pre-Compliance Testing
Speakers: Kenneth Wyatt (Wyatt Technical Services LLC), Dylan Stinson (Tektronix)
Location: Ballroom A
Track: 12. Electromagnetic Compatibility/Mitigating Interference
Session Type: Tutorial
Tuesday | 4:45 pm
Panel – 112-Gbps Package Challenges
Speakers: Hsinho Wu (Intel Corp.), Masashi Shimanouchi (Intel Corp.), Jenny Jiang (Intel Corp.), Richard Mellitz (Samtec), Yuriy Shlepnev (Simberian Inc.), Mike Resso (Keysight Technologies)
Location: Ballroom G
Track: 05. Advances in Materials & Processing for PCBs, Modules & Packages, 08. Optimizing High-Speed Serial Design
Session Type: Panel Discussion (Free)
Panel – Photonics Coming of Age: The Emergence of PDKs
Speakers: James Pond (Lumerical), Gilles Lamant (Cadence Design Systems), Mohamed Youssef (Mentor), Samir Chaudhry (TowerJazz), Rui Santos (SMART Photonics), Ashkan Seyedi (HPE)
Location: Ballroom D
Track: 03. Integrating Photonics & Wireless in Electrical Design
Session Type: Panel Discussion (Free)
Panel – The Case of the Closing Eyes: Optimizing 400-GbE Signal Integrity
Speakers: Chris Loberg (Tektronix, Inc.), Ransom Stephens (Ransom's Notes), Pavel Zivny (Tektronix, Inc.), Cathy Liu (Broadcom), Greg LeCheminant (Keysight), Martin Miller (Teledyne-LeCroy), Mark Marlett (Inphi)
Location: Ballroom E
Track: 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors
Session Type: Panel Discussion (Free)
Tuesday | 6:00 pm
Welcome Reception - Sponsored by: Keysight Technologies
Location: Santa Clara Ballroom, Hyatt Regency Santa Clara
Track: Welcome Reception
Session Type: Networking
Wednesday | 8:00 am
Speakers: Fadi Deek (Siemens), Eric Bogatin (Teledyne LeCroy Signal Integrity Academy)
Authors: Cristian Filip (Mentor, A Siemens Business), Melinda Piket-May (University of Coloardo at Boulder), Chuck Ferry (Mentor, A Siemens Business)
Location: Ballroom F
Track: 14. Modeling & Analysis of Interconnects, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Common Mode Filter Design to Reduce Radiation of PCIe 3 / 4 Signal
Speakers: Scott Lee (Quanta Computer), Eriksson Chuang (Quanta Computer)
Authors: Justin Wu (Quanta Computer), Jerry Syue (Quanta Computer)
Location: Ballroom A
Track: 12. Electromagnetic Compatibility/Mitigating Interference, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Mode Conversion & Its Impact on 112-Gbps PAM4 Systems
Speakers: Jason Chan (Cadence Design Systems, Inc.), Geoff Zhang (Xilinx)
Authors: Hong Anh (Xilinx), Min Huang (Xilinx)
Location: Ballroom C
Track: 08. Optimizing High-Speed Serial Design, 14. Modeling & Analysis of Interconnects
Session Type: Technical Session
Performance-Driven Voltage Regulator Module Specification for Optical Transport Network
Speakers: Xiaoping Liu (Intel Corporation), Dong-Myung Choi (Intel Corporation), Wendem Beyene (Intel Corporation)
Author: Ron Ho (Intel Corporation)
Location: Ballroom D
Track: 11. Power Integrity in Power Distribution Networks, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Testing Methodologies for Automotive Ethernet
Speakers: Marty Gubow (Keysight Technologies), Curtis Donahue (UNH-IOL), O.J. Danzy (Keysight Technologies)
Location: Ballroom B
Track: 13. Applying Test & Measurement Methodology
Session Type: Technical Session
Timing Assistant for Dynamic Voltage Drop Impact on Maximum Timing Pushout
Speakers: Norman Chang (ANSYS), Wentze Chuang (National Taiwan University)
Authors: Hao Zhuang (Google), Ganesh Tsavatapalli (ANSYS), Sankar Ramachandran (ANSYS), Rahul Rajan (ANSYS), Joao Jeada (ANSYS), Ying-Shiun Li (ANSYS), Yaowei Jia (ANSYS), Mathew Kaipanatu (ANSYS), Suresh Kumar Mantena (ANSYS), Ming-Chih Shih (ANSYS), Roger Jang (National Taiwan University)
Location: Ballroom E
Track: 15. Machine Learning for Microelectronics, Signaling & System Design
Session Type: Technical Session
Wednesday | 8:05 am
Speaker: Ching-Chao Huang (Ataitec)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
USB Type-C Technologies Physical and Protocol Layer Testing
Speaker: Mike Engbretson (Teledyne LeCroy)
Location: Mission City M2
Track: Sponsored Sessions
Session Type: Sponsored Session
Wednesday | 8:30 am
Get Your Game On for Next Generation DRAM: DDR5 and LPDDR5
Speaker: Perry Keller (Keysight Technologies)
Location: Great America 1
Track: Sponsored Sessions
Session Type: Sponsored Session
Wednesday | 9:00 am
A Comparative Study of Equalization Schemes for 112G PAM4 Links
Speaker: Yuchun Lu (Huawei Technologies)
Authors: Davide Tonietto (Huawei Canada), Henry Wong (Huawei), Weiyu Wang (Huawei), Pengchao Zhao (Huawei)
Location: Ballroom C
Track: 10. High-Speed Signal Processing, Equalization & Coding, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
Case Studies Isolating Types of Power Integrity Effects on Signal Integrity & Means of Mitigation
Speakers: Nitin Bhagwath (Mentor, A Siemens Business), Rula Bakleh (Samtec Teraspeed Consulting)
Location: Ballroom F
Track: 02. Chip I/O & Functional Block Modeling & Validation Solutions, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
Design Space Exploration with Polynomial Chaos Surrogate Models for Analyzing Large System Designs
Speaker: Majid Ahadi Dolatsara (Georgia Institute of Technology)
Authors: Ambrish Varma (Cadence Design Systems), Kumar Keshavan (Cadence), Madhavan Swaminathan (Georgia Institute of Technology)
Location: Ballroom B
Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Effect of Power Plane Inductance on Power Delivery Networks
Speakers: Shirin Farrahi (Cadence Design Systems), Mehdi Mechaik (Cadence Design Systems)
Authors: Ethan Koether (Oracle), Istvan Novak (Samtec)
Location: Ballroom E
Track: 11. Power Integrity in Power Distribution Networks, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Session Type: Technical Session
Speakers: Gustavo Blando (Samtec Inc), Scott McMorrow (Samtec Inc), Istvan Novak (Samtec)
Author: Ethan Koether (Oracle)
Location: Ballroom D
Track: 14. Modeling & Analysis of Interconnects
Session Type: Technical Session
Reflection Cancellation Design with Embedded Resistor for DDR Memory System
Speaker: Yang Wu (Intel)
Authors: Maoxin Yin (Intel), Jun Ye (Intel), Tao Xu (Intel)
Location: Ballroom A
Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 05. Advances in Materials & Processing for PCBs, Modules & Packages
Session Type: Technical Session
Speaker: Youngwoo Kim (KAIST, Terabyte Interconnection and Package Lab.)
Location: Ballroom G
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
Wednesday | 9:05 am
Faster Time to Insight Using Real Time Spectral Analysis of Power Rails
Speaker: Eric Bogatin (Teledyne LeCroy Signal Integrity Academy)
Location: Mission City M2
Track: Sponsored Sessions
Session Type: Sponsored Session
Measuring FPGAs: Signal Integrity, Power Integrity, and Rail Sequencing Probes
Speaker: Mike Schnecker (Rohde & Schwarz)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
Memory Options for High Performance Applications
Speakers: Sreeja Menon (Rambus), Frank Ferro (Rambus)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Wednesday | 9:20 am
PCI Express 5.0: Full Speed Ahead! Phy Layer Testing Challenges at 32GT/s
Speakers: Rick Eads (Keysight Technologies), Thorsten Goetzelmann (Keysight Technologies)
Location: Great America 1
Track: Sponsored Sessions
Session Type: Sponsored Session
Wednesday | 10:00 am
A Fast & Simple RFI Mitigation Method Without Compromising Signal Integrity
Speaker: Chulsoon Hwang (Missouri University of Science and Technology)
Authors: Qiaolei Huang (Missouri University of Science and Technology), Ling Zhang (Missouri University of Science and Technology), Yang Zhong (Missouri University of Science and Technology), Jagan Rajagopalan (Amazon lab126), Deepak Pai (Amazon lab126), Chen Chen (Amazon lab126), Amit Gaikwad (Amazon lab126), Jun Fan (Missouri University of Science and Technology)
Location: Ballroom E
Track: 12. Electromagnetic Compatibility/Mitigating Interference
Session Type: Technical Session
Design of 2.5D Interposer in High Bandwidth Memory & Through Silicon Via for High Speed Signal
Speaker: Bo Pu (Samsung Electronics)
Location: Ballroom A
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
Speakers: Yuriy Shlepnev (Simberian Inc.), Alex Manukovsky (Intel)
Location: Ballroom G
Track: 14. Modeling & Analysis of Interconnects
Session Type: Technical Session
Electrical Integrity for LPDDR5 Memory Technology
Speakers: Vishram Pandit (Intel Technology India Pvt. Ltd), Aiswarya Pious (Intel Corporation), Prabhat Ranjan (Intel Technology India Pvt Ltd), Arvindh Rajasekaran (Intel)
Authors: Kirankumar Kamisetty (Intel, Oregon USA), Jun Liao (Intel Hillsboro), Nagi Aboulenein, Christopher Cox (Intel Folsom)
Location: Ballroom B
Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
Enabling IBIS-AMI Simulations for Systems Containing PAM4 Retimers at 112 Gbps
Speakers: Fangyi Rao (Keysight Technologies), Hongtao Zhang (Xilinx)
Author: Geoff Zhang (Xilinx)
Location: Ballroom D
Track: 08. Optimizing High-Speed Serial Design, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Panel – Test Fixture Signal Integrity for 112G PAM-4: Lively Discussion on the Top Design Rules
Speakers: Alfred Neves (Wild River Technology), Heidi Barnes (Keysight Technologies), Jason Ellison (Amphenol)
Location: Ballroom C
Track: 13. Applying Test & Measurement Methodology
Session Type: Panel Discussion (Free)
TDECQ for PAM4 Optical Transmitters: Does it Really Work?
Speaker: Greg LeCheminant (Keysight)
Location: Ballroom F
Track: 03. Integrating Photonics & Wireless in Electrical Design, 13. Applying Test & Measurement Methodology
Session Type: Technical Session
Wednesday | 10:05 am
112Gbps ADC Based Long Reach SerDes
Speaker: Ken Dyer (Rambus)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Accelerating Oscilloscope Measurements through Real-Time fixture De-Embedding
Speaker: Mike Schnecker (Rohde & Schwarz)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
PCI Express 4.0 and 5.0 Electrical Compliance Test Challenges
Speaker: Patrick Connally (Teledyne LeCroy)
Location: Mission City M2
Track: Sponsored Sessions
Session Type: Sponsored Session
Wednesday | 10:15 am
Preparing to Test USB 3.2 and Next-gen Type-C Technologies
Speaker: Jit Lim (Keysight Technologies)
Location: Great America 1
Track: Sponsored Sessions
Session Type: Sponsored Session
Wednesday | 11:00 am
Baseline Wander: Systematic Approach to Rapid Simulation & Measurement
Speakers: Pavel Zivny (Tektronix), Vladimir Dmitriev-Zdorov (Mentor Graphics), Maria Agoston (Tektronix)
Location: Ballroom C
Track: 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Demistifying Edge Launch Connectors
Speakers: Raul Stavoli (Carlisile Interconnect Technologies), Davi Correia (Carlisle IT)
Author: Emad Soubh (Carlisle IT)
Location: Ballroom A
Track: 14. Modeling & Analysis of Interconnects
Session Type: Technical Session
Elimination of Highly Reflective Structures Through Sliding Decision Feedback Equalization
Speakers: Joseph Aday (Raytheon), Juli Olenick (Raytheon), Hongtao Zhang (Xilinx)
Authors: Torstein Molvik (Raytheon), Hannah Lee (Raytheon), Carolyn Henry (Raytheon), Geoff Zhang (Xilinx)
Location: Ballroom F
Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 10. High-Speed Signal Processing, Equalization & Coding
Session Type: Technical Session
Interconnect Design Practice Beyond 56-Gbps PAM4 System
Speakers: Greg Fu (Cisco), Sherman Chen (Cisco), Stephen Scearce (Cisco)
Location: Ballroom E
Track: 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
Modeling System Signal Integrity Dynamic to Achieve Optimal Memory Performance for DDR4 & Beyond
Speakers: Hing "Thomas" To (Xilinix), Changyi Su (Xilinx), Juan Wang (Xilinx)
Location: Ballroom B
Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
Speakers: Heidi Barnes (Keysight Technologies), Jason Ellison (Amphenol), Eric Bogatin (Teledyne LeCroy Signal Integrity Academy)
Authors: Jose Moreira (Advantest), Jim Nadolny (Samtec), Al Neves (Wild River Technology), Ching-Chao Huang (Ataitec), Patrick Murray (Anritsu), Mikheil Tsiklauri (Missouri University of Science and Technology), Neil Jarvis (Rohde & Schwarz)
Location: Ballroom D
Track: 13. Applying Test & Measurement Methodology
Session Type: Technical Session
Using Multiple Huygens' Boxes to Detect & Quantify the Coupling Path from Noise Source to Victim
Speaker: Antonio Ciccomancini Scogna (Huawei)
Authors: Liu Chen Jun (Huawei), Jiangqi He (Huawei), Cheng Weichang (Huawei)
Location: Ballroom G
Track: 12. Electromagnetic Compatibility/Mitigating Interference
Session Type: Technical Session
Wednesday | 11:05 am
Speakers: Steve Sekel (Keysight Technologies), Robert Sleigh (Keysight Technologies)
Location: Great America 1
Track: Sponsored Sessions
Session Type: Sponsored Session
Design & Development of DDR5 IBIS-AMI Models
Speakers: Douglas Burns (SiSoft (Signal Integrity Software, Inc.)), Justin Butterfield (Micron Technology Inc.), Randy Wolff (Micron Technology Inc.), Walter Katz (Signal Integrity Software Inc. (SiSoft))
Location: Mission City M1
Track: Sponsored Sessions
Session Type: Sponsored Session
Enable Innovation with Hardware-Enforced Security at the Core
Speaker: Ben Levine (Rambus)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Impedance Based Stability Margin Assessment Supports Analog, Power and Mixed Signal Applications
Speaker: Steve Sandler (PICOTEST.com)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
Solving PCI Express Issues Spanning Physical and Protocol Layers
Speaker: Patrick Connally (Teledyne LeCroy)
Location: Mission City M2
Track: Sponsored Sessions
Session Type: Sponsored Session
Wednesday | 12:00 pm
Keynote – 5G for Vehicle-to-X Communications
Keynote: Robert Heath (The University of Texas at Austin)
Location: Elizabeth A. Hangs Theater
Track: Keynote
Session Type: Keynote (Free)
Wednesday | 1:00 pm
5G Discussion & Networking with Keynoter Robert Heath
Speakers: Robert Heath (The University of Texas at Austin), Antonio Ciccomancini Scogna (Huawei), Suresh Subramaniam (Whizz Systems), Jose Moreira (Advantest)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Networking
Wednesday | 1:30 pm
Product Showcase: BSX Series BERTScope Bit Error Rate Tester
Location: Booth 539
Track: Product Showcase
Session Type: Product Showcase
Wednesday | 2:00 pm
A Review of Combiner/Divider PCB Design Topologies For 5G & WiGig ATE Applications
Speaker: Jose Moreira (Advantest)
Authors: Giovanni Bianchi (Advantest), Alexander Quint (Kalrsruhe Institute für Technologie)
Location: Ballroom D
Track: 03. Integrating Photonics & Wireless in Electrical Design
Session Type: Technical Session
Speakers: Cosmin Iorga (PIScanner.com), Cristian Filip (Mentor, A Siemens Business), Daniel de Araujo (Mentor, a Siemens Business), Chuck Ferry (Mentor, A Siemens Business)
Authors: Nitin Bhagwath (Mentor, a Siemens Business), Hans Klos (Sintecs), Arpad Muranyi (Mentor, A Siemens Business), Praveen Anmula (Mentor, A Siemens Business)
Location: Ballroom E
Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques
Session Type: Technical Session
COM & IBIS-AMI: How They Relate & Where They Diverge
Speaker: Hsinho Wu (Intel Corp.)
Authors: Masashi Shimanouchi (Intel Corp.), Mike Peng Li (Intel Corp.)
Location: Ballroom F
Track: 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
DFE Implementation & Optimization Considerations for Test & Measurement
Speaker: Kalev Sepp (Sepson Analytics LLC)
Location: Ballroom A
Track: 13. Applying Test & Measurement Methodology, 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors
Session Type: Technical Session
Exploring 56/112-Gbps Copper Interconnect Metrics Comparing Classic Methods with COM
Speakers: Chris Roth (Molex), Robert Schaefer (Keysight)
Authors: David Brunker (Molex), Mike Resso (Keysight), OJ Danzy (Keysight), Brent Hatfield (Molex), Joe Dambach (Molex), Michael Rost (Molex), Vivek Shah (Molex)
Location: Ballroom C
Track: 14. Modeling & Analysis of Interconnects, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
High Fidelity Simulation Using Measurement-based VRM Models
Speaker: Steve Sandler (Picotest.com)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Chiphead Theater (Free)
Memory Systems for AI and Leading-Edge Applications
Speaker: Steven Woo (Rambus)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Speaker: Brandon Jiao (Xilinx)
Authors: Romi Mayder (Xilinx), Ntsanderh C Azenui (Ansys), Andrew Wang (Ansys)
Location: Ballroom G
Track: 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques
Session Type: Technical Session
New Characterization Techniques for DDR5 Memory Generation and Beyond
Speaker: Saifee Jasdanwala (Tektronix)
Location: Mission City M1
Track: Sponsored Sessions
Session Type: Sponsored Session
PCI Express Refclk Jitter Compliance Using a Phase Noise Analyzer
Speaker: Gary Giust, PhD (SiTime)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
Product Showcase: R&S®RTP Oscilloscope
Location: Booth 623
Track: Product Showcase
Session Type: Product Showcase
Secrets To Successful Power Rail Measurements
Speaker: Eric Bogatin (Teledyne LeCroy Signal Integrity Academy)
Location: Mission City M2
Track: Sponsored Sessions
Session Type: Sponsored Session
Top-Down Jitter Specification Approach for HBM System Optimization
Speakers: Nanju Na (Xilinx), Thomas To (Xilinx), Anna Wong (Xilinx)
Location: Ballroom B
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
Wednesday | 2:30 pm
Product Showcase: EMC Shielding Solutions
Speaker: Robert Weber (Harwin)
Location: Booth 952
Track: Product Showcase
Session Type: Product Showcase
Wednesday | 2:50 pm
Apples-to-Apples PCB Laminate Characterization
Speakers: Bill Hargin (Z-zero), Don DeGroot (CCN)
Location: Ballroom D
Track: 05. Advances in Materials & Processing for PCBs, Modules & Packages, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
Characterization of Signal Integrity Using S-parameters
Speaker: Neil Jarvis (Rohde & Schwarz)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
Don't Let Ground Bounce Ruin Your Day
Speaker: Eric Bogatin (Teledyne LeCroy Signal Integrity Academy)
Location: Mission City M2
Track: Sponsored Sessions
Session Type: Sponsored Session
Exploring How 112G XSR Technology Enables Adoption of Optical Communication
Speakers: Nhat Nguyen (Rambus), Mondeep Thiara (Rambus)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
On the Minimization of PCB Differential Pair Skew or Its Effect
Speaker: Syed Bokhari (Fidus Systems Inc)
Location: Ballroom F
Track: 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques, 05. Advances in Materials & Processing for PCBs, Modules & Packages
Session Type: Technical Session
PCIe Gen 5 CEM Connector & Add-In Card PCB Design Optimizations
Speakers: Ying Li (Nvidia), Yifan Huang (Amphenol)
Authors: Stephen Smith (Amphenol), Alfred Key (NVIDIA), Abhijit S. Wander (Amphenol Corporation), Liu He (Amphenol Corporation), Yaping Zhou (Nvidia Corporation)
Location: Ballroom A
Track: 14. Modeling & Analysis of Interconnects, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
PDN Complexities & Design Strategy for Serdes Interfaces in Automotive/Workstation Applications
Speakers: Nithya Sankaran (Nvidia Corporation), Prathap Muthana (Nvidia Corporation)
Author: Sunil Sudhakaran (Nvidia Corporation)
Location: Ballroom B
Track: 11. Power Integrity in Power Distribution Networks, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Panel – System Challenges in Advanced Data Center & Machine Learning Platforms
Moderator: Thomas To (Xilinix)
Panelists: Raymond Nijseen (Achronix), Craig Hampel (Rambus), Larry Zu (Sarcina Technology)
Location: Ballroom E
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Session Type: Panel Discussion (Free)
Partitioning of TX & RX Feedforward Equalizer for 112-Gbps Serial Links
Speakers: Kevin Zheng (Xilinx Inc.), Hongtao Zhang (Xilinx)
Authors: Boris Murmann (Stanford University), Geoff Zhang (Xilinx)
Location: Ballroom G
Track: 08. Optimizing High-Speed Serial Design, 10. High-Speed Signal Processing, Equalization & Coding
Session Type: Technical Session
Spec-driven CTLE Model Synthesis Through Reinforcement Learning
Speaker: Zhaoyin Daniel Wu (Xilinx Inc)
Location: Ballroom C
Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
Understanding the Test Impacts to Today’s High Speed Digital Trends
Sponsor Speaker: Brig Asay (Keysight Technologies)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Sponsored Session
Wednesday | 3:00 pm
Product Showcase: SDS5000X Series Oscilloscopes
Speaker: Jason Chonko (Siglent Technologies)
Location: Booth 407
Track: Product Showcase
Session Type: Product Showcase
Wednesday | 3:45 pm
An Introduction to Crosstalk Measurements
Speaker: Dr. Chris Scholz (Rohde & Schwarz)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
Challenges of Testing V2X & Connectivity in Automotive
Speaker: Nikhil Kumar (Rohde & Schwarz)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Chiphead Theater (Free)
Next Generation Wireline Communication Interfaces
Speakers: Ravi Shivnaraine (Rambus), Saman Sadr (Rambus)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Panel – FEC for 112-Gbps High Speed Serial Links & Beyond
Speakers: Cathy Liu (Broadcom), Mike Li (Intel), Mike Steinberger (Sisoft), Steve Sekel (Keysight), Shaohua Yang (Broadcom Inc), Xiaoqing (Amanda) Dong
Location: Ballroom G
Track: 10. High-Speed Signal Processing, Equalization & Coding
Session Type: Panel Discussion (Free)
Panel – PCI Express Ecosystem: Getting Ready for 32 GT/s
Speakers: Steve Krooswyk (Samtec), Pegah Alavi (Keysight), Rita Horner (Synopsys), Mo Liu (Intel), Rick Eads (Keysight), Dean Gonzales (AMD), Alfred Key (NVIDIA)
Location: Ballroom C
Track: 08. Optimizing High-Speed Serial Design
Session Type: Panel Discussion (Free)
Panel – Real World Cloud & Machine Learning/AI Deployment for Hardware Design
Moderator: Christopher Cheng (Hewlett Packard Enterprise)
Speakers: Norman Chang (ansys), Wendem Beyene (Intel PSG), David White (Cadence), Chekib Akrout (Synopsys)
Location: Ballroom D
Track: 15. Machine Learning for Microelectronics, Signaling & System Design
Session Type: Panel Discussion (Free)
Practical On-Die Power Integrity Measurements
Speaker: Eric Bogatin (Teledyne LeCroy Signal Integrity Academy)
Location: Mission City M2
Track: Sponsored Sessions
Session Type: Sponsored Session
Wednesday | 4:00 pm
Product Showcase: Samtec 56 Gbps 7m ExaMAX® Backplane Cable Demonstration
Location: Booth 737
Track: Product Showcase
Session Type: Product Showcase
Wednesday | 4:45 pm
EMI Troubleshooting & Pre-Compliance Testing: Step-By-Step
Speakers: Kenneth Wyatt (Wyatt Technical Services LLC), Dylan Stinson (Tektronix)
Location: Chiphead Theater
Track: Chiphead Theater, 12. Electromagnetic Compatibility/Mitigating Interference
Session Type: Chiphead Theater (Free)
Wednesday | 5:00 pm
Thursday | 8:00 am
6.4Gb/s Single-Ended Transceiver Techniques for DDR5 Server Applications
Speaker: Gang Zhao (Huawei)
Authors: Tingting Pang (Huawei Technologies), Tianyu Liang (Huawei Technologies), Zhihua Xu (Huawei Technologies)
Location: Ballroom B
Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 10. High-Speed Signal Processing, Equalization & Coding
Session Type: Technical Session
A Statistical Based Approach to Pre-qualify Optical Modules for Radiated Emission Testing
Speaker: Philippe Sochoux (Juniper Networks)
Authors: Jing Li (Juniper Networks), Wei Zhang (Juniper Networks), David Pommerenke (Missiouri University of Science and Technology)
Location: Ballroom D
Track: 12. Electromagnetic Compatibility/Mitigating Interference
Session Type: Technical Session
Accelerating 56G PAM4 Link Equalization Optimization Using Machine Learning-based Analysis
Speakers: Ting Zhu (Hewlett Packard Enterprise), Yongjin Choi (Hewlett Packard Enterprise), Christopher Cheng (Hewlett Packard Enterprise), Jacky Chang (Hewlett Packard Enterprise Company)
Location: Ballroom G
Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
Speaker: Majid Ahadi Dolatsara (Georgia Institute of Technology)
Authors: Jose Hejase (IBM), Dale Becker (IBM), Madhavan Swaminathan (Georgia Institute of Technology)
Location: Ballroom A
Track: 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors, 15. Machine Learning for Microelectronics, Signaling & System Design
Session Type: Technical Session
Overcoming DDR5 Simulation Challenges
Speaker: John Ellis (Synopsys, Inc.)
Location: Ballroom F
Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
Practical Implementation of Testing 50-Gbps per Lane Effective Return Loss (ERL)
Speakers: Christopher DiMinico (MC Communications), Mike Klempa (UNH-IOL)
Authors: Curtis Donahue (UNH-IOL), O.J. Danzy (Keysight Technologies), Richard Mellitz (Samtec), Mike Resso (Keysight Technologies), Mike Sapozhnikov (Cisco Systems), Adee Ran (Intel)
Location: Ballroom C
Track: 13. Applying Test & Measurement Methodology, 14. Modeling & Analysis of Interconnects
Session Type: Technical Session
Wideband Jitter Tracking for Low Power Clock Forwarded I/O Links
Speaker: Armin Tajalli (Kandou Bus)
Location: Ballroom E
Track: 08. Optimizing High-Speed Serial Design, 10. High-Speed Signal Processing, Equalization & Coding
Session Type: Technical Session
Thursday | 8:05 am
Modeling and Simulation Challenges for 16Gbps GDDR6 Interfaces
Speakers: Chung Huang (Cadence), Kancy Robison (Cadence)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Thursday | 8:30 am
5G and Its Impact – From Server to Fronthaul
Speaker: Beate Hoehne (Keysight Technologies)
Location: Great America 1
Track: Sponsored Sessions
Session Type: Sponsored Session
Thursday | 9:00 am
Enabling 6.4-Gbps/pin LPDDR5 Interface Using Bandwidth Improvement Techniques
Speaker: Billy Koo (Samsung Electronics)
Location: Ballroom D
Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
Machine Learning Applications for Simulation & Modeling of 56 & 112-Gb SerDes Systems
Speakers: Adam J Norman (Intel), Alex Manukovsky (Intel)
Authors: Roee Bloch (Intel), Yaron Juniman (Intel), Zurab Khasidashvili (Intel)
Location: Ballroom B
Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 02. Chip I/O & Functional Block Modeling & Validation Solutions
Session Type: Technical Session
Power Integrity Planning & Simulations for a 2048 Processor Compute Card
Speaker: Jeffrey Smith (GHz Systems Inc.)
Location: Ballroom G
Track: 11. Power Integrity in Power Distribution Networks
Session Type: Technical Session
Quantifying Simulation Errors When Idealizing the Cross Section of Microstrips
Speaker: Erika Yazmin Teran Bahena (Instituto Nacional de Astrofisica Optica y Electronica)
Authors: Svetlana C. Sejas Garcia (ISOLA), Reydezel Torre Torres (Instituto Nacional de Astrofisica, Optica y Electronica)
Location: Ballroom E
Track: 13. Applying Test & Measurement Methodology, 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors
Session Type: Technical Session
Skew Measurement of High-speed Connector
Speaker: Zachary Su (Xpeedic)
Authors: Zhongmin Wei (ZTE Corporation), Maoxiang Wei (ZTE Corporation), Shunlin Zhu (ZTE Corporation), Bi Yi (ZTE Corporation)
Location: Ballroom A
Track: 14. Modeling & Analysis of Interconnects, 13. Applying Test & Measurement Methodology
Session Type: Technical Session
The Problem of Comparator Metastability in High-speed Wireline Receivers
Speaker: Sina Naderi Shahi (Huawei Technologies Canada)
Authors: MarcAndre LaCroix (Huawei Technologies Canada), Semyon Lebedev (Huawei Technologies Canada), Davide Tonietto (Huawei Canada)
Location: Ballroom C
Track: 08. Optimizing High-Speed Serial Design, 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors
Session Type: Technical Session
Thermoelectric Performance of Copper Clad Laminate
Speaker: Mark Shields (Nan Ya Plastics)
Location: Ballroom F
Track: 05. Advances in Materials & Processing for PCBs, Modules & Packages
Session Type: Technical Session
Thursday | 9:05 am
Analyzing LPDDR4X Interfaces using Circuit and Channel Simulation: A Case Study
Speaker: Snehamay Sinha (Texas Instruments)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Thursday | 9:20 am
A Practical Guide to Signal Integrity: From Simulation to Measurement
Speakers: Mike Resso (Keysight Technologies), Tim Wang Lee (Keysight Technologies)
Location: Great America 1
Track: Sponsored Sessions
Session Type: Sponsored Session
Thursday | 10:00 am
Speakers: Mike Li (Intel), Hsinho Wu (Intel Corp.), Masashi Shimanouchi (Intel)
Location: Ballroom D
Track: 10. High-Speed Signal Processing, Equalization & Coding
Session Type: Technical Session
Capacitor Insertion Methodology to Power Distribution Network for Improving Power Integrity
Speakers: Shigeaki Hahsimoto (Murata Manufacturing Co., Ltd.), Toru Nakura (Fukuoka University)
Author: Satoshi Komatsu (Tokyo Denki University)
Location: Ballroom C
Track: 11. Power Integrity in Power Distribution Networks
Session Type: Technical Session
Insertion Loss vs. Integrated Crosstalk Noise Metric for Link Analysis
Speaker: Shayan Shahramian (Huawei Canada)
Authors: Hossein Shakiba (Huawei Canada), Behzad Dehlaghi (Huawei Canada), David Cassan (Huawei Canada), Davide Tonietto (Huawei Canada)
Location: Ballroom E
Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
PCB Interconnect Modeling Demystified
Speaker: Bert Simonovich (Lamsim Enterprises Inc.)
Location: Ballroom F
Track: 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques, 05. Advances in Materials & Processing for PCBs, Modules & Packages
Session Type: Technical Session
Signal/Power Integrity Optimizations in an IoT Automotive Package
Speaker: Ben Silva (Intel Corporation)
Authors: Yan Fen Shen (Intel Corporation), Mohamed Eldessouki (Intel Corporation)
Location: Ballroom A
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Speakers: Yasin Damgaci (Hewlett Packard Enterprise), YongJin Choi (Hewlett Packard Enterprise), Christopher Cheng (Hewlett Packard Enterprise), Yuriy Shlepnev (Simberian Inc.), Nagaraj Godishala (Hewlett Packard Enterprise Company)
Location: Ballroom B
Track: 14. Modeling & Analysis of Interconnects
Session Type: Technical Session
Skew Metric & BER Testing Correlation for NRZ/PAM4 Signaling
Speaker: Mauro Lai (Intel Corporation)
Location: Ballroom G
Track: 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
Thursday | 10:05 am
Exposing Adaptive Equalization Functionality in 32 Gbps SerDes Receivers
Speaker: Greg Edlund (IBM)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
PCIe G3/G4 TX/RX Compliance Test and ready for G5
Speaker: Patrick Connally (Teledyne)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
Thursday | 10:15 am
Design of Electronic Control Systems for Quantum Computing
Speaker: Marc Almendros (Keysight Technologies)
Location: Great America 1
Track: Sponsored Sessions
Session Type: Sponsored Session
Thursday | 11:00 am
32-Gbps Channel Design for High Volume Platform Applications
Speaker: Mohiuddin Mazumder (Intel Corporation)
Authors: Anupriya Sriramulu (Intel Corporation), Prerana Singaraju (Intel Corporation), Raul Enriquez (Intel Corporation), Alaa Ali (Intel Corporation), Dan Froelich (Intel Corporation)
Location: Ballroom C
Track: 14. Modeling & Analysis of Interconnects, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Session Type: Technical Session
A Methodology for Performance Comparison of Center & Edge Sampling in Serial Links
Speaker: Hossein Shakiba (Huawei Canada)
Authors: David Cassan (Huawei Canada), Behzad Dehlaghi (Huawei Canada), Shayan Shahramian (Huawei Canada), Davide Tonietto (Huawei Canada)
Location: Ballroom A
Track: 08. Optimizing High-Speed Serial Design, 10. High-Speed Signal Processing, Equalization & Coding
Session Type: Technical Session
Distributed Decoupling Capacitors Application for PDN Designs of Fine Pitch BGA Products
Speakers: Shimon Morodooch (Harmonic Video Networks), Alex Manukovsky (Intel)
Authors: Amiram Jibly (Intel), Igal Fridman (Major Technology Company)
Location: Ballroom B
Track: 11. Power Integrity in Power Distribution Networks
Session Type: Technical Session
How the Braid Impedance of Instrumentation Cables Impact PI & SI Measurements
Speaker: Istvan Novak (Samtec)
Authors: Jim Nadolny (Samtec), Ethan Koether (Oracle), Gary Biddle (Samtec)
Location: Ballroom G
Track: 13. Applying Test & Measurement Methodology, 12. Electromagnetic Compatibility/Mitigating Interference
Session Type: Technical Session
Lowest-cost Communication with light from an IoT Device to Smartphone
Speaker: Laszlo Arato (NTB Buchs)
Location: Ballroom F
Track: 03. Integrating Photonics & Wireless in Electrical Design
Session Type: Technical Session
Panel – Future Issues in Power Integrity
Moderator: Mobashar Yazdani (Google)
Speakers: Eric Bogatin (Teledyne LeCroy Signal Integrity Academy), Henry Shrader (Analog.com), Brian Molloy (Infineon), Patrizio Vinciarelli (Vicor), Gregory Sizikov (Google)
Location: Ballroom E
Track: 02. Chip I/O & Functional Block Modeling & Validation Solutions
Session Type: Panel Discussion (Free)
Robust Simultaneous Switching Noise Prediction for Test using Deep Neural Network
Speakers: Bonita Bhaskaran (Nvidia Corporation), Seyed Nima Mozaffari (Nvidia Corporation)
Location: Ballroom D
Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 11. Power Integrity in Power Distribution Networks
Session Type: Technical Session
Thursday | 11:05 am
A Case Study in Streamlining the DC Analysis Workflow
Speaker: Songping Wu (Google)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Addressing PCIe Gen5 Test and Debug Challenges with Confidence
Speaker: Dan Froelich (Tektronix)
Location: Mission City M1
Track: Sponsored Sessions
Session Type: Sponsored Session
PCIe G4 TX/RX LEQ and JTOL Test Live Demo and How to Troubleshoot
Speaker: Hiroshi Goto (Anritsu)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
Reduce Simulation Complexity in DDR4 and Get Ready for DDR5
Speaker: Stephen Slater (Keysight Technologies)
Location: Great America 1
Track: Sponsored Sessions
Session Type: Sponsored Session
Thursday | 12:00 pm
Keynote: Gloria Lau (Uber)
Location: Elizabeth A. Hangs Theater
Track: Keynote
Session Type: Keynote (Free)
Thursday | 1:00 pm
Machine Learning Discussion & Networking with Keynoter Gloria Lau
Speakers: Gloria Lau (Uber), Christopher Cheng (Hewlett Packard Enterprise), Scott Wedge (Synopsys)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Networking
Thursday | 1:30 pm
Location: Booth 422
Track: Product Showcase
Session Type: Product Showcase
Thursday | 2:00 pm
100+ Gbps Ethernet Forward Error Correction (FEC) Analysis
Speaker: Cathy Liu (Broadcom)
Location: Ballroom G
Track: 10. High-Speed Signal Processing, Equalization & Coding, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
Speaker: Hiroshi Goto (Anritsu)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
A Novel Platform PI Isolation Design Approach, Upon IFPI with SPIM & UPIT
Speaker: Kinger Cai (Intel Corp.)
Location: Ballroom C
Track: 11. Power Integrity in Power Distribution Networks, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Session Type: Technical Session
Delivering 100-Gbps Solutions for Chip to Module & Direct Attach Cable Implementations
Speakers: Bruce Champion (TE Connectivity), Nathan Tracy (TE Connectivity)
Location: Ballroom F
Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Don't Judge a Bit Just by Its Fourier: 112-Gbps PAM4 Component Optimization & Selection
Speakers: Steve Krooswyk (Samtec), Madhumitha Rengarajan (Samtec)
Location: Ballroom B
Track: 08. Optimizing High-Speed Serial Design, 14. Modeling & Analysis of Interconnects
Session Type: Technical Session
Machine Learning Methods in High-Speed Channel Modeling
Speaker: Ken Wu (Google)
Author: Tianjian Lu (Google)
Location: Ballroom A
Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Session Type: Technical Session
Modeling and Simulating 112G SerDes
Speakers: Manuel Luschas (Cadence), Ken Willis (Cadence), Margaret Johnston (Cadence)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
Panel – Expanding the IoT Connectivity Options
Moderator: Christopher Wiltz (UBM)
Panelists: Laszlo Arato (NTB Buchs), Shravan Surineni (Qualcomm)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Chiphead Theater (Free)
Predicting Field Failure From Small Environmental Stresses
Speaker: Douglas C and Deborah Smith (D. C. Smith Consultants)
Location: Ballroom D
Track: 12. Electromagnetic Compatibility/Mitigating Interference, 13. Applying Test & Measurement Methodology
Session Type: Technical Session
Product Showcase: Samtec 112 Gbps PAM4 Flyover Cable Solution
Location: Booth 737
Track: Product Showcase
Session Type: Product Showcase
Speakers: Hyo-Soon Kang (Intel Corporation), Guang Chen (Intel)
Authors: Ashkan Hashemi (Intel Corporation), Wern Shin Choo (Intel Corporation), Wendem Beyene (Intel Corporation), David Greenhill (Intel)
Location: Ballroom E
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 11. Power Integrity in Power Distribution Networks
Session Type: Technical Session
Thursday | 2:50 pm
32Gbaud PAM4 BER and JTOL Test Live Demo (64Gbps per lane)
Speaker: James Morgante (Anritsu)
Location: Great America 2
Track: Sponsored Sessions
Session Type: Sponsored Session
A Novel Approach for ESD Generator Modeling Using Deep Neural Network
Speaker: Jayoung Yang (Samsung Electronics)
Authors: Jae-Young Shin (Samsung Electronics), Jaeho Lee (Samsung Electronics), Yoonna Oh (Samsung Electronics), Jin-Sung Youn (Samsung Electronics), Daehee Lee (Samsung Electronics), Seong-Jin Mun (Samsung Electronics), Chan-Seok Hwang (Samsung Electronics), Jong-Bae Lee (Samsung Electronics)
Location: Ballroom D
Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 12. Electromagnetic Compatibility/Mitigating Interference
Session Type: Technical Session
Advanced Package Design Sign-Off Reference Flow
Speakers: Sungwook Moon Ph.D. (Samsung Foundry Korea), Max Min Ph.D. (Samsung Foundry US)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
An Efficient Power & Signal Integrity Combo Simulation & Correlation for DDR4 & Beyond
Speakers: Thomas To (Xilinix), Juan Wang (Xilinx), Xi (Sean) Long (Xilinx)
Location: Ballroom F
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Session Type: Technical Session
EDA Tool-Based Methodology for Accurate Extraction ofOn-Die Capacitance & Resistance
Speakers: Karthik Chandrasekar (Intel PSG), Guang Chen (Intel)
Authors: Wendem Beyene (Intel PSG), Shaan Awasthi (Intel PSG), Anil Gundurao (Intel), Ying Fei Tan (Intel PSG)
Location: Ballroom E
Track: 11. Power Integrity in Power Distribution Networks, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Session Type: Technical Session
Speakers: Masashi Shimanouchi (Intel), Hsinho Wu (Intel Corp.)
Author: Mike Li (Intel)
Location: Ballroom G
Track: 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors
Session Type: Technical Session
Self-Correcting Modeling Enabled by a Recurrent Neural Network
Speakers: YongJin Choi (Hewlett Packard Enterprise), Sumon Dey (Hewlett Packard Enterprise Company)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Chiphead Theater (Free)
Thermal & SI/PI Co-Analysis to Quantify PCB Signal Loss Due to Temperature Variation
Speakers: Xiaoning Ye (Intel Corp), Hongfei Yan (Intel Corp)
Authors: Yinglei Ren (Intel Corp), Chunfei Ye (Intel Corp)
Location: Ballroom C
Track: 14. Modeling & Analysis of Interconnects, 04. System Co-Design: Modeling, Simulation & Measurement Validation
Session Type: Technical Session
Will My 25-Gb Channel Work for 112-Gb Signals?
Speakers: Alex Manukovsky (Intel), Adee Ran (Intel)
Authors: Amiram Jibly (Intel), Stas Litski (Intel)
Location: Ballroom A
Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 08. Optimizing High-Speed Serial Design
Session Type: Technical Session
Thursday | 3:00 pm
Product Showcase: Rohde & Schwarz
Location: Booth 623
Track: Product Showcase
Session Type: Product Showcase
Thursday | 3:45 pm
Panel – 112-Gbps Electrical Interfaces: An OIF Update on CEI-112G
Speakers: Brian Holden (Kandou Bus SA), Steve Sekel (Keysight Technologies), Cathy Liu (Broadcom), Nathan Tracy (TE Connectivity)
Location: Ballroom G
Track: 08. Optimizing High-Speed Serial Design, 10. High-Speed Signal Processing, Equalization & Coding
Session Type: Panel Discussion (Free)
Panel – Ultra Short Reach (XSR) Electrical I/O Interfaces at 112G: Why, Challenges & Solutions
Moderator: Mike Li (Intel)
Panelists: Thomas Liljeberg (Intel, Silicon Photonics), Edward Frlan (Semtech, High-Speed I/O Link), Brian Taylor (Facebook, Optical Network), Robert Stone (Broadcom, Switch Architecture), Valery Kugel (Juniper, Silicon and System)
Location: Ballroom C
Track: 03. Integrating Photonics & Wireless in Electrical Design
Session Type: Panel Discussion (Free)
Panel – Which Model When? Succeeding with IBIS-AMI
Moderator: Donald Telian (SiGuys)
Panelists: Walter Katz (Signal Integrity Software, Inc.), Michael Mirmak (Intel Corp.), Justin Butterfield (Micron Technology Inc.)
Speaker: Ken Willis (Cadence)
Location: Ballroom D
Track: 02. Chip I/O & Functional Block Modeling & Validation Solutions, 08. Optimizing High-Speed Serial Design
Session Type: Panel Discussion (Free)
System Planning and Management for 3D Designs
Speaker: TV Narayanan (Cadence)
Location: Great America 3
Track: Sponsored Sessions
Session Type: Sponsored Session
What Every Scope User Needs to Know About Transmission Lines
Speaker: Eric Bogatin (Teledyne LeCroy Signal Integrity Academy)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Chiphead Theater (Free)
Thursday | 4:00 pm
Product Showcase: Samtec 56 Gbps PAM4 Active Product Demonstrator
Location: Booth 737
Track: Product Showcase
Session Type: Product Showcase
Thursday | 4:45 pm
Chiphead Comedy: The Funny Interconnect
Speaker: Taiwan Tim (Taiwan Tim Comedy)
Location: Chiphead Theater
Track: Chiphead Theater
Session Type: Chiphead Theater (Free)
Thursday | 5:00 pm