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All Sessions Speakers My Schedule
Tuesday | 8:00 am

Welcome Breakfast Bites

Location: Mission City Ballroom Foyer

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Tuesday | 9:00 am

Boot Camp – Getting to 32 Gb/S: Training on Very High Speed Differential Signaling

Lee Ritchey (President, Speeding Edge)

Location: Ballroom G

Pass Type: All Access Pass, Alumni All Access Pass, Boot Camp Pass

Track: Boot Camp

Audience Level: Introductory

Format: Full Day Boot Camp

Boot Camp – Pragmatic Signal Integrity

Todd Westerhoff (VP, Semiconductor Relations, SiSoft), Michael Steinberger (Lead Architect, Serial Channel Products, SiSoft), Donald Telian (Independent Consultant, SiGuys), Eric Brock (Principal Member of Technical Staff , SiSoft)

Location: Ballroom E

Pass Type: All Access Pass, Alumni All Access Pass, Boot Camp Pass

Track: Boot Camp

Audience Level: Introductory

Format: Full Day Boot Camp

Boot Camp – Test & Measurement Techniques

O.J. Danzy (Senior RF and Microwave Application Engineer, Keysight Technologies), Heidi Barnes (Senior Application Engineer, Keysight Technologies), Mike Resso (Signal Integrity Application Scientist i, Keysight Technologies), Steve Sekel (400G Solutions Specialist, OIF PLL Interop WG Chair, Keysight Technologies), Bob Schaefer (R&D Project Manager and Master Engineer for the Signal Integrity Group, Keysight Technologies), Robert Sleigh (Strategic Planner, Keysight Technologies), Luis Boluna (Senior Application Engineer for High Speed Digital Systems, Keysight Technologies), Brig Asay (Director of Strategic Planning , Keysight Technologies)

Location: Great America Meeting Room 2

Pass Type: All Access Pass, Alumni All Access Pass, Boot Camp Pass

Track: Boot Camp

Audience Level: Introductory

Format: Full Day Boot Camp

Tutorial – Design & Verification for High-Speed I/Os at 10 to 112 Gbps With Jitter, Signal Integrity, and Power Optimization

Mike Peng Li (Fellow, Intel)

Location: Ballroom C

Pass Type: All Access Pass, Alumni All Access Pass

Track: 09. Measurement, Simulation, and Optimization of Jitter, Noise, and Timing to Minimize Errors

Audience Level: All

Format: 3-Hour Tutorial

Tutorial – Designing for Ultra Low Power: Opening the Door to Energy Harvesting

Brian Zahnstecher (Principal, PowerRox)

Location: Ballroom D

Pass Type: All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: All

Format: 3-Hour Tutorial

Tutorial – Introduction to Machine Learning and Its Applications in High Speed Serial Link Design & Analysis

Zao Liu (Staff Design Engineer, Xilinx)

Location: Ballroom A

Pass Type: All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Format: 3-Hour Tutorial

Tuesday | 12:00 pm

Keynote – SI/PI & EMI Challenges: Looking Ahead Through 2023

Steve Sandler (Managing Director, Picotest), Istvan Novak (Senior Principal Engineer, Oracle), Eric Bogatin (Adjunct Professor, University of Colorado), Alfred Neves (Chief Technologist, Wild River Technology), Kenneth Wyatt (Sr. EMC Engineer, Wyatt Technical Services LLC)

Location: Mission City Ballroom

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Keynote (Free)

Audience Level: All

Format: 45-Minute Keynote

Tuesday | 12:45 pm

Lunch (complimentary for special pass types)

Location: Mission City Ballroom M1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass

Tuesday | 1:30 pm

Tutorial – A Step by Step Guide for Channel Modeling & Simulation That Correlates to Lab Measurement for 25Gb NRZ & 56Gb PAM4 Applications

Alex Manukovsky (Technical lead, SI/PI team, Intel), Amiram Jibly (Senior SI Engineer, Intel)

Location: Ballroom D

Pass Type: All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Format: 3-Hour Tutorial

Tutorial – Introduction to IBIS-AMI

Todd Westerhoff (VP, Semiconductor Relations, SiSoft), Walter Katz (Chief Scientist, SiSoft), Mike LaBonte (Senior IBIS-AMI Specialist, SiSoft)

Location: Ballroom C

Pass Type: All Access Pass, Alumni All Access Pass

Track: 02. Mixed Signal Modeling: Algorithmic and Simulation Solutions

Audience Level: Introductory

Format: 3-Hour Tutorial

Tutorial – Principles of Power Integrity for PDN Design

Larry Smith (Principal Engineer, Qualcomm), Eric Bogatin (Signal Integrity Evangelist, Teledyne LeCroy)

Location: Ballroom B

Pass Type: All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: All

Format: 3-Hour Tutorial

Tutorial – Radiated Emissions: Product Evaluation & Pre-Compliance Testing

Kenneth Wyatt (Principal Consultant, Wyatt Technical Services LLC)

Location: Ballroom A

Pass Type: All Access Pass, Alumni All Access Pass

Track: 12. Electromagnetic Compatibility and Mitigating Interference

Audience Level: All

Format: 3-Hour Tutorial

Tuesday | 4:45 pm

Panel – Machine Learning Advances in Electronic Design

Christopher Cheng (Distinguished Technologist, Hewlett-Packard Enterprise), Paul Franzon (Cirrus Logic Distinguished Professor, North Carolina State University), David White (Senior Director of R&D, Cadence Design Systems), Madhavan Swaminathan (John Pippin Chair Professor, Georgia Institute of Technology), Sashi Obilisetty (R&D Director, Synopsys)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Format: 75-Minute Panel Discussion

Panel – The Case of the Closing Eyes: Is PAM the Answer?

Chris Loberg (Sr. Technical Marketing Manager, Tektronix, Inc.), Ransom Stephens, Ph.D. (Signal Integrity Sage, Ransom's Notes), Martin Miller (Chief Scientist, Teledyne-LeCroy), Greg LeCheminant (Measurement Applications Specialist, Digital Communications Analysis, Internet Infrastructure Solutions, Keysight Technologies), Pavel Zivny (Domain Expert, Tektronix), Cathy Liu (R&D Director, Broadcom Limited), Mike Peng Li (Fellow, Intel), Mark Martlett (Principal Engineer, Inphi)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 09. Measurement, Simulation, and Optimization of Jitter, Noise, and Timing to Minimize Errors

Audience Level: All

Format: 75-Minute Panel Discussion

Panel – USR Alliance: The MCM is the New PCB

Brian Holden (VP of Standards, Kandou Bus SA), Yaniv Kopelman (CTO, Networking, Marvell Semiconductor, Inc.), Amin Shokrollahi (CEO, Kandou Bus SA), Gidi Navon (Principal Engineer, Marvell Semiconductor, Inc.)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 01. Signal & Power Integrity at the Single-Multi Die, Interposer, and Packaging Level

Audience Level: All

Format: 75-Minute Panel Discussion

Tuesday | 6:00 pm

Welcome Reception Sponsored by Keysight Technologies

Location: Hyatt Regency Santa Clara Ballroom

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass

Track: Reception (Free)

Audience Level: All

Wednesday | 8:00 am

An Introduction To Non‐Invasive Current Estimation (NICE)

Jonathan Fasig (Principal Engineer, Mayo Clinic), Christopher White (Senior Engineer, Mayo Clinic), Barry Gilbert (Director, Mayo Clinic), Clifton Haider (Deputy Director, Mayo Clinic)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: All

Format: 45-Minute Technical Session

Decompositional Analysis of Copper Roughness Effect and Complex Permittivity – Part II

Nicke Svee (Sr Specialist R&D, Ericsson AB), Jun Wang (signal integrity engineer, Ericsson AB), Davood Khoda (Signal Integrity design engineer, Ericsson AB)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: All

Format: 45-Minute Technical Session

Electrical Performance Analysis of Low-Cost and Ultra-Thin Glass Interposers/Packages: Advantages, Challenges and Solutions.

Youngwoo Kim (Ph.D Candidate, KAIST, Terabyte Interconnection and Package Lab.)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 05. Advances in Materials and Processing for PCBs, Modules, and Packages

Audience Level: All

Format: 45-Minute Technical Session

Feedforward Equalizer Location Study for High Speed Serial Systems

Kevin Zheng (Research Assistant, Stanford University), Boris Murmann (Professor, Stanford University), Hongtao Zhang (Senior Staff Design Engineer, Xilinx Inc.), Geoff Zheng (Distinguished Engineer , Xilinx Inc.)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: Intermediate

Format: 45-Minute Technical Session

Reduction of Mode Conversion in SerDes Links

Mehdi Mechaik (Staff Application Engineer, Cadence Design Systems)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 12. Electromagnetic Compatibility and Mitigating Interference

Audience Level: All

Format: 45-Minute Technical Session

Signaling and Performance Challenges and Solutions for Next-Generation OIF CEI-112G-VSR "Chip-to-Module" Interfaces

Mike Peng Li (Fellow, Intel), Hsinho Wu (SOC Design Engineer, Intel), Masashi Shimanouchi (SOC Design Engineer, Intel), Nathan Tracy (Technologist, TE)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: Advanced

Format: 45-Minute Technical Session

Temperature- and Geometry-dependent analysis of high-speed PCB Traces

Soumya De (SI Engineer, Cisco), Han Gao (SI Engineer, Cisco), Jian Liu (SI Engineer, Cadence), Yaochao Yang (Principal Engineer, Cisco), An-Yu Kuo (Sr. Group Director, Cadence), Miroslav Grubic (SI Engineer, Cisco)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 06. Applying PCB Design and Simulation Tools

Audience Level: Introductory

Format: 45-Minute Technical Session

Wednesday | 8:30 am

Measuring Power Rail Noise Impact on Clock Jitter

Mike Schnecker (Business Development Manager, Rhode & Schwarz USA, Inc.)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Single Pulse Response: SI Analysis in the Blink of an Eye

Chun-ting "Tim" Wang Lee (Application Engineer for High Speed Digital applications in the EEsof EDA Group, Keysight Technologies)

Location: Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Wednesday | 9:00 am

40 GHz PCB Interconnect Validation: Expectations vs Reality

Marko Marin (Sr, Electronics Design Engineer, Infinera), Yuriy Shlepnev (President, Simberian Inc.)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: All

Format: 45-Minute Technical Session

Designing High Current 48V to Core Voltage Converters

Steve Sandler (Managing Director, Picotest)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: All

Format: 45-Minute Technical Session

Determining the Onset Frequency for the Metal Surface Roughness Loss

Reydezel Torres-Torres (Senior Researcher, INAOE), Svetlana C. Sejas-García (SI Engineer, Isola), Chudy Nwachukwu (SI Engineer, Intel)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: All

Format: 45-Minute Technical Session

Fiber Weave Effect: Modeling, measurements, challenges and its impact on differential insertion loss for weak and strong-coupled differential transmission lines

Amendra Koul (Technical Leader - Signal Integrity, Cisco systems inc), Kartheek Nalla (Signal Integrity Engineer, Cisco Systems Inc.), David Nozadze (Signal Integrity Intern, Cisco Systems Inc.), Mike Sapozhnikov (Sr. Signal Integrity Manager, Cisco Systems Inc.), Yaochao Yang (Principal Engineer/Technical Director , Cisco Systems Inc.)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 05. Advances in Materials and Processing for PCBs, Modules, and Packages

Audience Level: All

Format: 45-Minute Technical Session

In-depth SI and PI Analysis of Chip-to-chip Interconnect Using Silicon Bridge

Changwook Yoon (System SI/PI Engineer, Intel), Guang Chen (SI/PI engineer, Intel), Hyosoon Kang (SI/PI Engineer, Intel Corporation), Ashkan Hashemi (SI/PI engineer, Intel), Janani Chandrasekhar (SIPI Engineer , Intel), David Greenhill (Senior Director, Intel), Wendem Beyene (Technical Director, Rambus)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 07. Advanced IO Interface Design for Memory and 2.5D/3D/SiP Integrations

Audience Level: All

Format: 45-Minute Technical Session

Mechanism Finding and Possible Mitigating Solutions of Serial-TX-Introduced Interference Picked Up by LC-PLL

Zhaoyin Daniel Wu (Senior Staff Engineer, Xilinx Inc), Parag Upadhyaya (Director, SERDES Technology Group, Xilinx Inc), Geoff Zhang (Distinguished Engineer, Xilinx Inc), Ade Bekele (Senior Staff Design Engineer, Xilinx Inc.), Santiago Asuncion (Product Application Engineer, Xilinx Inc.), Yohan Frans (Senior Engineering Director, Xilinx, Inc), Ken Chang (Vice President, SerDes Technology, Xilinx Inc.)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 01. Signal & Power Integrity at the Single-Multi Die, Interposer, and Packaging Level

Audience Level: All

Format: 45-Minute Technical Session

Tale of a Differential Pair Measurement

Gustavo Blando (Senior Principal Engineer, Oracle Corporation), Istvan Novak (Senior Principle Engineer, Oracle Corporation), Eben Kunz (Senior Hardware Engineer, Oracle Corporation), Gregory Truhlar (Senior Hardware Engineer, Oracle Corporation)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: Introductory

Format: 45-Minute Technical Session

Wednesday | 9:20 am

Ethernet MACs in 400/800GbE Applications

Mohit Gupta (Senior Director Product Marketing, Rambus), Don Cober (Principal Engineer, Ethernet IP, CoMira)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

In-Situ De-embedding

Ching-Chao Huang (President , AtaiTec Corporation)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Stop Wasting Time and Money by Struggling with Data Analytics While Designing T&M Experiments

Brad Doerr (R&D Manager Digital & Photonics Center of Excellence, Keysight Technologies), Ailee Grumbine (Strategic Product Planner – Data Analytics, Keysight Technologies)

Location: Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Wednesday | 10:00 am

112G Electrical System Performance Study based on an improved Salz SNR Methodology

Xiaoqing Dong (System engineer, Huawei Technologies), Gongxian Jia (System Engineer , Huawei Technologies), Vivek Shah (Engineering Director , Molex LLC), Kingle Wang (Signal Integrity Engineer , Molex LLC), Chunxing huang (System engineer, Shenzhen Zhongzeling Electronics), Yu Bi (Sr. Signal Integrity Engineer , Molex LLC)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: Intermediate

Format: 45-Minute Technical Session

A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics

Vladimir Dmitriev-Zdorov (Principal Engineer, Mentor Graphics, a Siemens Business), Bert Simonovich (President, Lamsim Enterprises Inc), Igor Kochikov (Principal Engineer, Mentor Graphics, a Siemens Business)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: Intermediate

Format: 45-Minute Technical Session

Accurate and Fast RFI Prediction Based on Dipole Moment Sources and Reciprocity

Qiaolei Huang (PhD student, Missouri Univ of Sci& Tech), Takashi Enomoto (EMC Engineer, Sony GM&O), Shingo Seto (EMC Engineer, Sony GM&O), Kenji Araki (Deputy General Manager and Principal Engineer, Sony GM&O), Jun Fan (Professor, Missouri Univ of Sci& Tech), Chulsoon Hwang (Assistant Professor, Missouri Univ of Sci& Tech)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 12. Electromagnetic Compatibility and Mitigating Interference

Audience Level: All

Format: 45-Minute Technical Session

Behavioral FEC Models for High Speed Serial Link BER Simulation

Hsinho Wu (Design Engineer, Intel), Mike Li (Fellow, Intel), Masashi Shimanouchi (Design Engineer, Intel)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: Intermediate

Format: 45-Minute Technical Session

LPDDR4X (4266 Mbps) FOWLP-PoP vs Conventional-PoP Co-SI/PI System Analysis

Sunil Gupta (Ph.D., Qualcomm Technologies, Inc.), Will Navaja (Staff, Qualcomm Technologies, Inc.), Patrick Zilaro (Senior Staff, Qualcomm Technologies, Inc.)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: All

Format: 45-Minute Technical Session

Spectral Methods for Signal & Power Integrity

Scott Wedge (Principal Engineer, Synopsys, Inc.)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 02. Mixed Signal Modeling: Algorithmic and Simulation Solutions

Audience Level: Intermediate

Format: 45-Minute Technical Session

The Gap Between Eye "Mask" Compliance, BER and BER contours.

Martin Miller (Chief Scientist, Teledyne-LeCroy)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: Intermediate

Format: 45-Minute Technical Session

Wednesday | 10:15 am

112G - Designer's Trade-offs and Challenges for a Successful 56/112G High-Speed SerDes Design

Saman Sadr (VP High Speed SerDes IO, Rambus)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Advanced

Format: 40-Minute Technical Session

EMI Debugging: Tracking Down Sources of Interference

Mike Schnecker (Business Development Manager, Rhode & Schwarz USA, Inc.), Randy White (Strategic Oscilloscope Planner, Rohde and Schwarz)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

What’s New in Testing 400G/PAM4 Transmitter Designs?

Robert Sleigh (Strategic Planner– Network Data Centers, Keysight Technologies), Greg LeCheminant (Measurement Applications Specialist, Digital Communications Analysis, Internet Infrastructure Solutions, Keysight Technologies)

Location: Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Wednesday | 11:00 am

A Comparative Analysis of Power Delivery Network (PDN) Noise with Data Bit Inversion (DBI) Scheme for VDD Termination Reference and Ground Termination Reference IO Systems

Qian Wang (Design Engineer, Xilinx, Inc), Penglin Niu (Sr. Design Engineer Manager, Xilinx, Inc), Thomas To (Technical Director, Xilinx, Inc)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 01. Signal & Power Integrity at the Single-Multi Die, Interposer, and Packaging Level

Audience Level: All

Format: 45-Minute Technical Session

Characterization and Optimization of Via Designs Using Z-parameters

Hee-Soo LEE (Lead Application Developer, Keysight Technologies), Nathan Hirsch (PCB Engineer, Monsoon Solutions, Inc), Orlando Bell (VP of Engineering, GigaTest Labs)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: All

Format: 45-Minute Technical Session

Effect of Conductor Profile on the Impedance and Capacitance of Transmission Lines

Allen F Horn III (Research Fellow, Rogers Corporation), Christopher J. Caisse (R&D Engineer, Rogers Corporation), Patricia A. LaFrance (Sr. Engineering Assistant, Rogers Corporation), Kristi Pance (Sr. Principal Innovator, Rogers Corporation Innovation Center), James C. Rautio (CEO, Sonnet Software)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 05. Advances in Materials and Processing for PCBs, Modules, and Packages

Audience Level: All

Format: 45-Minute Technical Session

Effective Return Loss for 112G and 56G PAM4

Richard Mellitz (Distinguished Engineer, Samtec)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: Intermediate

Format: 45-Minute Technical Session

Glass Weave Skew Effect on 56Gbps PAM4 System

Xu Yan (Signal Integrity Engineer, Cisco System Inc.), Stephen Scearce (Hardware Engineering Manager, Cisco Systems), Baoshu Xu (Technical Leader , Cisco System Inc.), Greg Fu (Technical Leader, Cisco System Inc.), Tonghao Ding (Signal Integrity Engineer, Cisco System Inc.), Andrew Bell (Applications Engineering Manager, WUS Printed Circuits)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 05. Advances in Materials and Processing for PCBs, Modules, and Packages

Audience Level: All

Format: 45-Minute Technical Session

Measuring S-parameter Models of Power Delivery Networks in FPGA Systems by Using an Embedded Multi-port Vector Network Analyzer

Cosmin Iorga (Engineer, NoiseCoupling.com)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: All

Format: 45-Minute Technical Session

PCIe Connector and Interface Development for 25-32Gbps/Channel Bandwidth

Lei Shan (RSM, IBM Corporation, T J Watson Research Center), Daniel Friedman (RSM, IBM Corp., T J Watson Research Center), Craig Kennedy (Engineer , Amphenol Corporation), Warren Persak (Manager, Amphenol Corporation), Kevin Lau (Sales Manager and Product Manager, Amphenol Corporation)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Format: 45-Minute Technical Session

Wednesday | 11:05 am

112G XSR - The Die to Die Interface IP Potential

Mondeep Thiara (Senior Director Product Marketing, Rambus)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Building IBIS-AMI Models for DDR5 Applications

Todd Westerhoff (VP, Semiconductor Relations, SiSoft)

Location: Mission City Ballroom M1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Measuring and Interpreting Impedance for Power Integrity

Steve Sandler (Founder and CEO, Picotest)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Recent Learnings in Bringing Up the First 400G Links

Steve Sekel (400G Solutions Specialist, Internet Infastructure Solutions, Keysight Technologies)

Location: Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Wednesday | 12:00 pm

Keynote – How Do We Make Autonomous Vehicles Safe Enough?

Todd Hubing (Professor Emeritus of Electrical and Computer Engineering, Clemson University)

Location: Mission City Ballroom

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Keynote (Free)

Audience Level: All

Format: 45-Minute Keynote

Wednesday | 1:00 pm

Panel – The Impact of Machine Learning on Solution Space Analysis: Are Circuit and Channel Simulation Obsolete?

Ken Willis (Product Engineering Architect, Cadence Design Systems), Chris Cheng (Distinguished Technologist, Hewlett-Packard Enterprise), Kumar Keshavan (Senior Software Architect, Cadence Design Systems), Madhavan Swaminathan (John Pippin Chair Professor, Georgia Institute of Technology), Dale Becker (Chief Engineer of Electronic Packaging Integration, IBM), Ken Wu (Staff Hardware Engineer and Signal/Power Integrity Manager, Google)

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Format: 1-Hour Chiphead Theater Session

Wednesday | 1:15 pm

Expo Tour – Autonomous Vehicle Technology

Chris Wiltz (Senior Editor, Design News, UBM)

Location: Networking Lounge (Booth 1435)

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Expo Tour (Free)

Format: 1-Hour Expo Tour

Wednesday | 2:00 pm

Designing DC-Blocking Capacitor Transitions to Enable 56Gbps NRZ & 112Gbps PAM4

Scotty Neally (Signal Integrity Consultant, Samtec Inc.), Scott McMorrow (CTO Signal Integrity Products, Samtec Inc.)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: Intermediate

Format: 40-Minute Technical Session

EMI Analysis and Mitigation Techniques for 56G PAM4 Signaling

Xiangyang Jiao (EMC Design Engineer, Cisco Systems), Ling Zhang (Co-op Student, Missouri University of Science and Technology), Xiao Li (EMC Design Engineer, Cisco Systems), Soumya De (SI Engineer, Cisco Systems), Alpesh Bhobe (EMC Design Manager/Technical Leader, Cisco Systems)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 12. Electromagnetic Compatibility and Mitigating Interference

Audience Level: All

Format: 40-Minute Technical Session

Fixture De-embedding in Higher Crosstalk Situations

Jon Martens (Fellow, Anritsu)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: Intermediate

Format: 40-Minute Technical Session

How Low Loss PCB Material Impact DDR Channel Margin

Yin Maoxin (Analog Engineer, Intel Corp.), Yinglei Ren (Analog Engineer, Intel Corp.), Yanwu Wang (Analog Engineer, Intel Corp)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 06. Applying PCB Design and Simulation Tools

Audience Level: All

Format: 40-Minute Technical Session

How the Embedded Active IC Structure could Apply to Wearable Application with Ultra-thin and Low-RFI

Bumhee Bae (Senior Engineer, Samsung Electronics), JongWan Shim (Senior Engineer, Samsung Electronics), Younho Kim (Engineer, Samsung Electronics), HyungGeun Kim (Principal Engineer, Samsung Electronics), HarkByeong Park (Principal Engineer, Samsung Electronics)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 01. Signal & Power Integrity at the Single-Multi Die, Interposer, and Packaging Level

Audience Level: All

Format: 40-Minute Technical Session

How to Manage TDMA Power Amplifier Switching Noise Coupling to Audio CODECs in Mobile Phones

Shinyoung Park (Ph.D. Candidate, Korea Advanced Institute of Science and Technology), Jinwook Song (Ph.D. Candidate, Korea Advanced Institute of Science and Technology), Subin Kim (Ph.D. Candidate, Korea Advanced Institute of Science and Technology), Youngwoo Kim (Ph.D. Candidate, Korea Advanced Institute of Science and Technology), Joungho Kim (Professor, Korea Advanced Institute of Science and Technology)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: All

Format: 40-Minute Technical Session

Materials Used in Gigabit Cable and Their Electrical Characteristics

Patrick Casher (VP - Engineering, Lorom)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: All

Format: 40-Minute Technical Session

Memory Controller Integration and Verification

Frank Ferro (Senior Director Product Marketing, Rambus), Joe Rodriguez (Product Marketing Engineer, NW Logic)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

PCI Express Gen4 Clock Jitter Measurements Using Phase Noise Methodology

Gary Giust (Founder and Owner, Jitterlabs)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

PCIe Gen4 Compliance: From Physical to Protocol Layer

Patrick Connally (Technical Marketing Manager, Teledyne LeCroy), John Wiedemeier (Sr. Product Marketing Manager for Protocol Solutions Group, Teledyne LeCroy)

Location: Mission City Ballroom M1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Wednesday | 2:15 pm

How Interconnects Work: The Easy Way

Yuriy Shlepnev (President, Simberian Inc.)

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Format: 1-Hour Chiphead Theater Session

Wednesday | 2:50 pm

Characterization of Signal Integrity Using S-parameters

Neil Jarvis (RF and Microwave Applications Engineer, Rohde & Schwarz USA, Inc.)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Fast Hierarchical Optimization Method for High Speed Channel Design Using Channel Operating Margin (COM)

Bo Pu (Senior Engineer, Samsung Electronics)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 06. Applying PCB Design and Simulation Tools

Audience Level: All

Format: 40-Minute Technical Session

Fast Resonance Reduction Using Eigenmode Solution and Custom Metrics

Davi Correia (Signal Integrity Engineer, Carlisle IT), Stephan Baker (Electrical Consulting Engineer, Simutech), Alexandra Haser (Senior Industry Standards Engineer, Molex), Michael Rowlands (Signal Integrity Engineer, IO Connector Group, Amphenol)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: Advanced

Format: 40-Minute Technical Session

HBM2 - Advancing Data Center and Network Bandwidth

Frank Ferro (Senior Director Product Marketing, Rambus)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Hacking Skew Measurement

Clement Luk (Signal integrity engineer, Hirose Electric), Jeremy Buan (Signal Integrity manager, Hirose Electric), Tadashi Ohshida (High Speed Engineering Manager, Hirose Electric), Ping Jen Wang (Signal Integrity Engineer, Hirose Electric), Yuta Oryu (Signal Integrity Engineer, Hirose Electric), Ching-Chao Huang (President, AtaiTec), Neil Jarvis (Application Engineer, Rohde & Schwarz)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: All

Format: 40-Minute Technical Session

Non-conventional Approaches for Maximizing Current Capacity of a PDN

Nitin Bhagwath (Technical Marketing Engineer, Mentor Graphics), Doug Brooks (President, Ultracad), Joseph Aday (Principal Engineer, Raytheon), Robin Bornoff (Market Development Manager, Mentor Graphics), Praveen Anmula (Product Architect, Mentor Graphics), Robert Carter (Vice President of Business Development and Technology, Oak-Mitsui Technologies), Patrick Carrier (Engineering Planning Manager, Mentor Graphics)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 05. Advances in Materials and Processing for PCBs, Modules, and Packages

Audience Level: Introductory

Format: 40-Minute Technical Session

Power Integrity for 32 Gb/s SERDES Transceivers

Heidi Barnes (Applications Engineer, Keysight Technologies), Jack Carrel (Applications Engineer, Xilinx), Steve Sandler (Founder and CEO, Picotest)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: Intermediate

Format: 40-Minute Technical Session

Root-cause Analysis and Resolution of Mobile System Failure through Chip-Package-System Co-simulation

Byunghyun Lee (Senior Engineer, Samsung Electronics), Woncheol Baek (Senior Engineer, Samsung Electronics), Youngsoo Lee (Senior Product Manager, CPS Solutions, ANSYS)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: All

Format: 40-Minute Technical Session

Signaling Considerations for 112G Long Reach Applications

Rick Brooks (Manager, Hardware Engineering, Cisco Systems Inc), Kelvin Qiu (Manager, Hardware Engineering, Cisco Systems Inc), Zao Liu (Staff Design Engineer, Xilinx Inc), Geoff Zhang (Distinguished Engineer and Supervisor, Xilinx Inc)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: Intermediate

Format: 40-Minute Technical Session

Time-Saving Debug Solutions for Testing PCIe Gen4 and Beyond

Joe Allen (Market Segment Lead for Server & Storage, Tektronix)

Location: Mission City Ballroom M1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Wednesday | 3:00 pm

Speed Networking – Machine Learning

Location: Speed Networking Lounge

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Networking Session (Free)

Audience Level: All

Format: 1-Hour Networking Session

Wednesday | 3:45 pm

An Introduction to Crosstalk Measurements

Dr. Chris Scholz (Product Manager, Rohde and Schwarz USA, Inc.)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

High-Speed Memory Architectures for Next Generation Applications

Steve Woo (Vice President, Systems and Solutions, Office of the CTO, Rambus)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Format: 40-Minute Technical Session

Panel – CEI-112G: Every. Last. Thing. Matters.

David Stauffer (Principal Engineer, Kandou Bus SA), Steve Sekel (400G Solutions Specialist, OIF PLL Interop WG Chair, Keysight Technologies), Ed Frlan (OIF TC Vice Chair, Semtech), Nathan Tracy (OIF VP Marketing, TE Connectivity)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Format: 75-Minute Panel Discussion

Panel – Continued Innovation in a World Challenged by the Slowing of Moore's Law

Joe Macri (Corporate Vice President, Product Chief Technology officer and Corporate Fellow, AMD), Bob O'Donnell (President, Founder and Chief Analyst , TECHnalysis Research), Rob Aitken (Fellow & Director of Technology , ARM), Rory McInerney (VP in the Platform Engineering Group and Director of the Server Development Group, Intel)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Format: 75-Minute Panel Discussion

Panel – IBIS-AMI: New Users, New Uses

Donald Telian (SI Consultant, SiGuys), Steven Parker (Principal Member of Technical Staff, Global Foundries), Todd Westerhoff (VP, Semiconductor Relations, SiSoft), Stephen Scearce (Hardware Engineering Manager, Cisco Systems), Ken Willis (Product Engineering Architect, Cadence Design Systems), Michael Mirmak (Senior SI Technical Lead, Intel)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 02. Mixed Signal Modeling: Algorithmic and Simulation Solutions

Audience Level: All

Format: 75-Minute Panel Discussion

Panel – The 400G Ethernet Turn: The Rise and Fall of the Eye Diagram

Pavel Zivny (Domain Expert, Tektronix), Adee Ran (Principal Engineer, Intel), Greg LeCheminant (Engineer, Keysight Technologies), Cathy Liu (R&D Director, Broadcom Limited), Eldad Bar-Lev (Staff Signal Integrity Engineer, Marvell Israel Ltd.), Richard Mellitz (Principal Engineer, Samtec)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: All

Format: 75-Minute Panel Discussion

Wednesday | 4:30 pm

How to Keep Via to Via Coupling From Ruining Your Day

Eric Bogatin (Signal Integrity Evangelist, Teledyne LeCroy), Fadi Deek (Corporate Application Engineer, Mentor Graphics)

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Format: 45-Minute Chiphead Theater Session

Wednesday | 5:00 pm

Booth Bar Crawls

Location: Expo Hall

Pass Type: 2-Day Pass, All Access Pass, Boot Camp Pass, Expo Pass

Track: Happy Hour (Free)

Audience Level: All

Format: 1-Hour Networking Session

Happy Hour

Location: Expo Hall

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Happy Hour (Free)

Audience Level: All

Wednesday | 5:30 pm

Passport Program Prize Announcements

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Format: 45-Minute Chiphead Theater Session

Thursday | 8:00 am

A Convolution Technique for Verifying Acceptable PTPX Current Waveforms for PDN Voltage Droops

Larry Smith (Principal Engineer, Qualcomm), Yi Cao (Staff Engineer, Qualcomm)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: Intermediate

Format: 45-Minute Technical Session

A Study of Forward Error Correction Codes for SAS Channel

Haitao (Tony) Xia (Distiguished Engineer, Broadcom Limited), Aravind Nayak (Principle Engineer, Broadcom Limited), Haotian Zhang (Principle Engineer, Broadcom Limited), Jun Yao (Staff Engineer, Etopus), Bruce Wilson (Director, Broadcom Limited)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: All

Format: 45-Minute Technical Session

Advanced Packaging Technology and Die-Package-PCB Co-Design for 56G NRZ FPGA

Hong Shi (Director, Package Development, Xilinx), Siow Chek Tan (., Xilinx Inc), Yohan Frans (., Xilinx, Inc), Hongtao Zhang (., Xilinx, Inc.), Jack Carrel (., Xilinx,Inc), Sai Lalith Chaitanya Ambatipudi (., Xilinx, Inc.), David Mahashin (., Xilinx, Inc)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: All

Format: 45-Minute Technical Session

Effective Link Equalizations using FIR, CTLE, FFE, DFE, and FEC for Serial Links at 112 Gbps and Beyond

Hsinho Wu (Design Engineer, Intel Corp.), Masashi Shimanouchi (Design Engineer, Intel Corp.), Mike Peng Li (Fellow, Intel Corp.)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Format: 45-Minute Technical Session

Novel Method of Precision Channel Modeling for High Speed Serial 56Gb Interfaces

Alex Manukovsky (Technical lead, SI/PI team, Intel), Zurab Khasidashvili (Senior software engineer, Intel), Yaron Juniman (Senior SI Engineer, Intel)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: All

Format: 45-Minute Technical Session

PDO Methodology to Verify SI and Reduce EMI Risks in Mobile Devices

Antonio Ciccomancini Scogna (Principal Engineer, Samsung), Nitin Srivastava (Senior Engineer, Samsung Electronics), Junho Lee (Principal Engineer, Samsung Electronics), Hwanwoo Shim (Principal Engineer, Samsung Electronics)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 12. Electromagnetic Compatibility and Mitigating Interference

Audience Level: Intermediate

Format: 45-Minute Technical Session

Thursday | 8:30 am

Complete Automation of Type-C Devices

Brian Fetz (Senior Solutions Manager for Display and Measurement Technologies , Keysight Technologies)

Location: Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Temperature- and Geometry-Dependent Analysis of High-Speed PCB Traces

Soumya De (SI Engineer, Cisco Systems), Yaochao Yang (Principal Engineer/Technical Director , Cisco Systems Inc.), Han Gao (SI Engineer, Cisco), Miroslav Grubic (SI Engineer, Cisco), An-Yu Kuo (Sr. Group Director, Cadence), Jian Liu (SI Engineer, Cadence)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Thursday | 9:00 am

A New Machine Learning Approach for Optimization and Tuning of Integrated Systems

Hakki Torun (PhD Candidate, Georgia Institute of Technology), Madhavan Swaminathan (John Pippin Chair Professor, Georgia Institute of Technology)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: All

Format: 45-Minute Technical Session

Efficient Sensitivity-Aware Assessment of High-Speed Links Using PCE and Implications for COM

Torsten Reuschel (Research Assistant, Hamburg University of Technology), Jayaprakash Balachandran (Technical Lead, Cisco Systems Inc), Ömer Yildiz (Research Assistant, Hamburg University of Technology), Cristian Filip (Product Marketing Manager, Mentor Graphics), Nitin Bhagwath (Technical Marketing Manager, Mentor Graphics), Bidyut Sen (Principal Engineer, Cisco Systems Inc), Christian Schuster (Professor / Head of Institute, Hamburg University of Technology)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Format: 45-Minute Technical Session

How Spatial Variation of Voltage Regulator Output Impedance Depends on Sense Point and Bypass Capacitor Locations

Istvan Novak (Senior Principle Engineer, Oracle), Alejandro ‘Alex’ Miranda (Senior Hardware Engineer, Oracle)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: Introductory

Format: 45-Minute Technical Session

LPDDR4 IO Modeling and System Correlation for Critical Targeted Data Speed and Data Through-Put

Changyi Su (design engineer, Xilinx), Hing Y "Thomas" To (Technical Director, Xilinx), Yong Wang (Sr. Director, Xilinx)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 07. Advanced IO Interface Design for Memory and 2.5D/3D/SiP Integrations

Audience Level: All

Format: 45-Minute Technical Session

Performance Analysis for Next Generation PCIe Interface

Mehdi Mechaik (Staff Application Engineer, Cadence Design Systems), Blake Bader (Application Engineer Director, Cadence Design Systems)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: All

Format: 45-Minute Technical Session

Reliability: Embedded Capacitance Designs versus Discrete Components for High Speed

Robert Carter (Vice President of Business Development and Technology, Oak-Mitsui Technologies)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 05. Advances in Materials and Processing for PCBs, Modules, and Packages

Audience Level: All

Format: 45-Minute Technical Session

Simulation Instead of Measurement for Tx Compliance Testing of I/Os Supporting Multiple Physical Interfaces and Multi-channel Devices

Alex Manukovsky (Technical lead, SI/PI team, Intel), Yaron Juniman (Senior SI Engineer, Intel)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: All

Format: 45-Minute Technical Session

Thursday | 9:20 am

DDR-4400 IP Model Development Using AMI Builder

Chung Huang (Design Engineering Director, Cadence), Zhen Mu (Product Engineering Architect, Cadence)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

PCI Express 5.0 and the Latest Standards

Rick Eads (Principal PCI Express Program Manager, Internet Infastructure Solutions, Keysight Technologies), Pegah Alavi (Senior Applications Engineer, Keysight Technologies)

Location: Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Thursday | 10:00 am

A Method for Calculating Component-Level Crosstalk Contributions to Channel Crosstalk

Brent Rothermel (Hardware Engineer, Intel Corporation), Jeremy Stephens (Principal Engineer, Intel Corporation), Chien-Ping Kao (Sr. Signal and Power Integrity Engineer, Intel)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: Intermediate

Format: 45-Minute Technical Session

Applying IBIS-AMI Techniques to DDR4/5 Analysis

Todd Westerhoff (VP, Semiconductor Relations, SiSoft), Doug Burns (VP, Consulting, SiSoft), Eric Brock (Principal Member of Technical Staff , SiSoft)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 02. Mixed Signal Modeling: Algorithmic and Simulation Solutions

Audience Level: Intermediate

Format: 45-Minute Technical Session

Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard

Ken Willis (Product Engineering Architect, Cadence Design Systems), Kumar Keshavan (Senior Software Architect, Cadence Design Systems), Ambrish Varma (Senior Principal Software Engineer, Cadence Design Systems)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Format: 45-Minute Technical Session

Equalization requirements for DDR5

Nitin Bhagwath (Technical Marketing Engineer, Mentor Graphics), Randy Wolff (Principal Engineer, Micron), Vladimir Dmitriev-Zdorov (Principal Engineer, Mentor Graphics), Shinichiro Ikeda (Manager of Custom SoC Development, Socionext), Arpad Muranyi (Principal Engineer, Mentor Graphics), Chuck Ferry (Product Marketing Manager, Mentor Graphics), Eiji Fujine (Hardware Engineer, Socionext), Ryo Shibata (Hardware Engineer, Socionext), Yumiko Sugaya (Hardware Engineer, Socionext), Megumi Ono (Hardware Engineer, Socionext)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 07. Advanced IO Interface Design for Memory and 2.5D/3D/SiP Integrations

Audience Level: All

Format: 45-Minute Technical Session

Fixture Crosstalk Assessment Test Fixture For VNA Measurement

Hansel Dsilva (Signal Integrity Engineer, Intel, Corporation), Se-Jung Moon (Senior Hardware Engineer, Intel, Corporation), Xiaoning Ye (Principal Engineer, Intel, Corporation), Michael Brownell (Technical Lead, Intel, Corporation)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: All

Format: 45-Minute Technical Session

High Gain Low Complexity Low Latency FEC Codes for Ethernet and Backplane Applications

Yuchun Lu (Senior Engineer, Huawei Technologies)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: All

Format: 45-Minute Technical Session

TDECQ: Understanding compliance testing for PAM4 optical transmitters

Greg LeCheminant (Engineer, Keysight Technologies), David Leyba (Engineer, Keysight Technologies)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 03. Integrating Photonic and Electronic Signaling

Audience Level: All

Format: 45-Minute Technical Session

Thursday | 10:15 am

200/400G PAM4 BER Test Solution (IEEE 802.3, CEI, IBTA)

Hiroshi Goto (Digital/Optical Business Development Manager, Anritsu)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Advanced IC Packaging Trends and Their Impact on EDA Tools

John Park (Product Management Director, Cadence)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Establish a Robust Signal Integrity Measurement and Simulation Workflow

Mike Resso (Signal Integrity Application Scientist, Keysight Technologies), Chun-ting "Tim" Wang Lee (Application Engineer for High Speed Digital applications in the EEsof EDA Group, Keysight Technologies)

Location: Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Thursday | 11:00 am

16Gb/s and Beyond with Single-Ended I/O in High-Performance Graphics Memory

Tim Hollis (Distinguished Member of the Technical Staff – Signal Integrity R&D Lead, Micron Technology, Inc.), Salman Jiva (Sr. Business Development Mgr – Compute / Networking Business Unit, Micron Semiconductor Products), Martin Brox (Fellow - Design, Micron Semiconductor GmbH), Wolfgang Spirkl (Distinguished Member of the Technical Staff – Product Engineering, Micron Semiconductor GmbH), Thomas Hein (Senior Member of the Technical Staff - Design, Micron Semiconductor GmbH), Dave Ovard (Senior Member of the Technical Staff – Signal Integrity R&D, Micron Technology, Inc.), Roy Greeff (Senior Member of the Technical Staff – Signal Integrity R&D, Micron Technology, Inc.), Dan Lin (Senior Member of the Technical Staff – Signal Integrity R&D, Micron Technology, Inc.), Michael Richter (Principal Engineer - Design, Micron Semiconductor GmbH), Peter Mayer (Principal Engineer – Product Engineering, Micron Semiconductor GmbH), Walt Moden (Principal Engineer – Package Design, Micron Technology, Inc.), Maksim Kuzmenka (Senior Engineer - Design, Micron Semiconductor GmbH), Mani Balakrishnan (Senior Engineer - Design, Micron Semiconductor GmbH), Milena Ivanov (Senior Engineer - Design, Micron Semiconductor GmbH), Manfred Plan (Senior Engineer - Design, Micron Semiconductor GmbH), Marcos Alvarez Gonzalez (Senior Engineer – Product Engineering, Micron Semiconductor GmbH), Bryce Gardiner (Senior Engineer – System Signal Integrity, Micron Technology, Inc.), Dong Soon Lim (Senior Engineer – Package Signal Integrity, Micron Technology, Inc.)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 07. Advanced IO Interface Design for Memory and 2.5D/3D/SiP Integrations

Audience Level: All

Format: 45-Minute Technical Session

A NIST Traceable PCB Kit for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics

Jose Moreira (Senior Staff Engineer, Advantest), Heidi Barnes (Senior Application Engineer, Keysight Technologies), Eric Bogatin (Dean, Teledyne LeCroy Signal Integrity Academy, Teledyne LeCroy), Mikheil Tsiklauri (Research Associate Professor, Missouri University of Science and Technology), Ching-Chao Huang (President, Ataitec), Jim Nadolny (Engineering Manager, Samtec), Jason Ellison (Signal Integrity Engineer, The Siemon Company), Se-Jung Moon (Senior Hardware Engineer, Intel), Volker Herrmann (RF & Microwave Senior Application Engineer, Rohde & Schwarz)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: Intermediate

Format: 45-Minute Technical Session

An Efficiently-Generated Via Model For PCB Crosstalk and Link Analysis

Michael Degerstrom (Electical Engineer, Mayo), Chad Smutzer (Senior Engineer, Mayo Clinic), Christopher White (Senior Engineer, Mayo Clinic), Barry Gilbert (Director, Mayo Clinic), Clifton Haider (Deputy Director, Mayo Clinic)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 06. Applying PCB Design and Simulation Tools

Audience Level: All

Format: 45-Minute Technical Session

End-to-End System-Level Simulations with Repeaters for PCIe Gen4/CCIX: How to Deal with Temperature

Alexander Hanchett (WW Product Marketing, High Speed Signal Conditioning, Texas Instruments), Yongyao Li (Principle Engineer, Huawei), Casey Morrison (Systems Engineering Manager, Texas Instruments), Fangyi Rao (Master R&D Engineer, Keysight), Hong Ahn (SerDes Technology Group, Xilinx), Van Zhu (Senior Integrity Engineer, Huawei), Cindy Cui (Application Engineer , Keysight), Geoff (Geoffrey) Zhang (Distinguished Engineer , Xilinx), Khalid Jakoush (Application Engineer, Texas Instruments)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 14. Modeling and Analysis of Interconnects

Audience Level: Advanced

Format: 45-Minute Technical Session

IBIS-AMI for PCI Express Gen 4

Greg Edlund (Senior Engineer, IBM), Mehdi Mechaik (Staff Application Engineer, Cadence Design Systems), Ken Willis (Product Engineering Architect, Cadence Design Systems), Ambrish Varma (Senior Principal Software Engineer, Cadence Design Systems), Kumar Keshavan (Senior Software Architect, Cadence Design Systems)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 09. Measurement, Simulation, and Optimization of Jitter, Noise, and Timing to Minimize Errors

Audience Level: Intermediate

Format: 45-Minute Technical Session

JCOM is Setting New Goals: Accuracy, Custom Device Models, IP Protection, Advance Optimization Methods

Vladimir Dmitriev-Zdorov (Principal Engineer, Mentor Graphics, A Siemens Business), Pablo Acosta (Staff Design Engineer, Analog Devices, Inc), Ingvar Karlsson (Senior Specialist Signal Integrity for Ericsson AB, Ericsson AB), Cristian Filip (Marketing Manager, Mentor Graphics, A Siemens Business), Chuck Ferry (Product Marketing Manager, Mentor Graphics, A Siemens Business), Mikael Stahlberg (Euro Application Engineer, Mentor Graphics, A Siemens Business)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: Intermediate

Format: 45-Minute Technical Session

Statistical-Based RE DCD Jitter Analysis in High Speed NAND Flash Memory

Sayed Mobin (Senior Manager, Western Digital), Cindy Cui (Application Engineer , Keysight)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: All

Format: 45-Minute Technical Session

Thursday | 11:05 am

56G PAM4 BER Test Live Demo

James Morgante (Anritsu Field Application Engineer, Anritsu)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Getting the Most Out of DDR4 and Preparing for DDR5

Perry Keller (Lead Digital Applications and Standards Program, Memory Applications Program Manager, Keysight Technologies)

Location: Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

HSSO - Physical Structure Optimization for High-Speed Interconnects

Jack Stone (Senior Signal and Power Integrity Engineer, Intel)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Thursday | 12:00 pm

Keynote – New Horizons: Journey to Pluto and Beyond

Alice Bowman (New Horizons Mission Operations Manager, Johns Hopkins University Applied Physics Laboratory)

Location: Mission City Ballroom

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Keynote (Free)

Audience Level: All

Format: 45-Minute Keynote

Thursday | 1:00 pm

What Happens in a Patent Lawsuit?

John Strawn (Consultant, Ph.D., S Systems), Thomas Millikan (Partner, Perkins Coie LLP)

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Format: 75-Minute Chiphead Theater Session

Thursday | 1:15 pm

Expo Tour – Enabling the Internet of Things

Chris Wiltz (Senior Editor, Design News, UBM)

Location: Networking Lounge (Booth 1435)

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Expo Tour (Free)

Format: 1-Hour Expo Tour

Thursday | 2:00 pm

Advanced Techniques for Analysis of PAM4 Signals in Low SNR Environments

Rick Eads (Engineer, Keysight Technologies)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 09. Measurement, Simulation, and Optimization of Jitter, Noise, and Timing to Minimize Errors

Audience Level: All

Format: 40-Minute Technical Session

Balancing Excess Reactance in Test Fixtures to Minimize Interconnect Channel Distortion - Part II

Gert Havermann (Signal Integrity Engineer, HARTING AG&Co.KG)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: All

Format: 40-Minute Technical Session

Brand-New Electrical and Thermal Co-Simulation Analysis

Abby Wei-Chien Chou (Senior Engineer, Foxconn), Daniel Ying-Tso Lai (Senior Deputy Manager, Foxconn), Gino Chun-Jen Chen (Senior Deputy Manager, Foxconn)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Chip-level Power Integrity Methodology for High-Speed Serial Links

Shayan Shahramian (Analog/System IC Design Engineer, Huawei Canada – HiLink), Behzad Dehlaghi (Analog/System IC Design Engineer, Huawei Canada – HiLink), Yue Yin (MASc Candidate, University of Toronto), Rudy Beerkens (Staff Engineer, Huawei Canada – HiLink), David Cassan (Technical Director, Huawei Canada – HiLink), Davide Tonietto (Director of SerDes Development, Huawei Canada – HiLink), Anthony Chan Carusone (Professor, University of Toronto)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: All

Format: 40-Minute Technical Session

Elastomeric-based Interconnects Use Waveguide Structures to Enable Terabit Networks by Minimizing Physical Layer Pathologies

Mike Resso (Signal Integrity Applications Scientist, Keysight Technologies), Davi Correia (Senior Signal Integrity Engineer, Carlisle Interconnect Technologies)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: Advanced

Format: 40-Minute Technical Session

Examining System Challenges When Implementing Next Generation Datacenter Input/Output (I/O) Connectivity

Nathan Tracy (Technologist, TE)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: All

Format: 40-Minute Technical Session

Machine Learning based Source Reconstruction for RF Desensitization Analysis

Qiaolei Huang (PhD student, Missouri Univ of Sci& Tech), Yuan Chen (Master Student, Missouri Univ of Sci& Tech), Chulsoon Hwang (Assistant Professor, Missouri Univ of Sci& Tech), Jun Fan ( Professor, Missouri Univ of Sci& Tech)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 12. Electromagnetic Compatibility and Mitigating Interference

Audience Level: All

Format: 40-Minute Technical Session

PCI Express GEN3, GEN4 and GEN5 Physical Layer Test Requirements and Procedures

Patrick Connally (Technical Marketing Manager, Teledyne LeCroy)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

The Protocol of the PHY: High-Speed Ethernet Designs Require Protocol Knowledge and Awareness

David Rodgers (Sr. Program Marketing Manager, Teledyne LeCroy - PSG)

Location: Mission City Ballroom M1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Thursday | 2:30 pm

Speed Networking – Signal Integrity

Location: Speed Networking Lounge

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Networking Session (Free)

Audience Level: All

Format: 1-Hour Networking Session

Test Instruments as the Machine in Machine Learning: Some Practical Examples

Chris Cheng (Distinguished Technologist, Hewlett-Packard Enterprise), Ting Zhu (Hewlett Packard Enterprise), YongJin Choi (Master Technologist, Hewlett-Packard Enterprise)

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Format: 45-Minute Chiphead Theater Session

Thursday | 2:50 pm

A New Platform Power Integrity Design Approach with SPIM and UPIT

Xingjian Kinger Cai (Engineering Manager, Intel), Jimmy Hsiao (Hardware Power Customer Engineer, Intel), Denis Chen (PAE SI/PI Engineer, Intel), Chi-te Chen (Staff Power Integrity Engineer, Intel), Yun Ling (Sr. Principle Engineer, Intel), Steven Yun Ji (Sr. Manager Engineering, Intel)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Concurrent 3DIC Power Supply Analysis for Xilinx SSIT SerDes Interface

Ling Yang (Design Engineer, Xilinx Inc), KangWei Lai (Director of Engineer, Xilinx Inc.), Anusha Prakash (Application Engineer, Ansys)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 01. Signal & Power Integrity at the Single-Multi Die, Interposer, and Packaging Level

Audience Level: All

Format: 40-Minute Technical Session

High Speed Serial Bus Receiver Test Solution (PCIe G4, Thunderbolt, USB 3.0)

Mike Engbretson (Chief Technical Engineer, Granite River Labs)

Location: Great America Meeting Room 2

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Improved Engineering Analysis in FEC System Gain for 56G PAM4 Applications

Xiaoqing Dong (System engineer, Huawei Technologies), Geoff (Geoffrey) Zhang (Distinguished Engineer , Xilinx), Chunxing Huang (System Engineer, Shenzhen Zhongzeling Electronics Co., Ltd.)

Location: Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: Intermediate

Format: 40-Minute Technical Session

Improving TDECQ and SNDR for Better Characterization of Serial Data Signals, and Path From Mask Test to TDEC, SNDR, and TDECQ Measurements

Maria Agoston (Principal Engineer, Tektronix), Pavel Zivny (Domain Expert, Tektronix), Richard Mellitz (Principal Engineer, Samtec), Kan Tan (Principal Engineer, Tektronix), Jan Peeters Weem (Principal Engineer, Tektronix)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 09. Measurement, Simulation, and Optimization of Jitter, Noise, and Timing to Minimize Errors

Audience Level: Advanced

Format: 40-Minute Technical Session

Link BER Estimation for ADC-based SerDes Design Using IBIS-AMI Simulations

Hongtao Zhang (Senior Staff Design Engineer, Xilinx), Fangyi Rao (Master R&D Engineer, Keysight Technologies), Geoff Zhang (Distinguished Engineer and Supervisor, Xilinx)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 02. Mixed Signal Modeling: Algorithmic and Simulation Solutions

Audience Level: Intermediate

Format: 40-Minute Technical Session

Measuring Current and Current Sharing of DC-DC Converters

Istvan Novak (Senior Principle Engineer, Oracle), Peter Pupalaikis (Vice President of Technology Development, Teledyne LeCroy), Lawrence Jacobs (Manager, Probe Development Group, Teledyne-LeCroy)

Location: Ballroom A

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: Introductory

Format: 40-Minute Technical Session

Novel Approach to Address Common-mode Noise on High Speed IOs

Aruna Bathini (Analog Engineer, Intel corporation), Anoop Karunan (Technical Lead and Manager, Intel), Manjunath J (Analog Engineer, Intel Corporation), Aruna Kumar (Senior Analog Design Engineer, Intel Corporation)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 12. Electromagnetic Compatibility and Mitigating Interference

Audience Level: Advanced

Format: 40-Minute Technical Session

Novel Isolation Scheme for Mitigating PDN Coupling

Alex Waizman (Sr. PE, Intel Corporation), Vishram Pandit (Platform Architect, Intel Corporation), Martin Peterburg Alzaradel (Senior Analog Engineer , Intel), Vijay Kasturi (Sr. Analog Engineer, Intel Corporation)

Location: Ballroom E

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: Intermediate

Format: 40-Minute Technical Session

Thursday | 3:30 pm

Secrets to Successful Power Rail Measurements

Eric Bogatin (Signal Integrity Evangelist, Teledyne LeCroy)

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Audience Level: All

Format: 45-Minute Chiphead Theater Session

Thursday | 3:45 pm

DDR5 Modeling Using Automated IBIS-AMI Modeling Technology

Randy Wolff (Principal Engineer, Micron)

Location: Great America 3

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Session (Free)

Audience Level: Intermediate

Format: 40-Minute Technical Session

Panel – 400G Test & Measurement Ready for the New Challenges Ahead

Paul Brooks (Lab & Production Business Unit, Viavi Solutions), David Rodgers (Ethernet Alliance Marketing Chair, Sr. Product Marketing Manager, Teledyne LeCroy), Pavel Zivny (Domain Expert, Tektronix), Ed Sayre (Distinguished System Engineer, Samtec)

Location: Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 13. Applying Test and Measurement Methodology

Audience Level: All

Format: 75-Minute Panel Discussion

Panel – How to Avoid getting Totally Skewed: Glass-Weave Skew in High-Speed Design

Bill Hargin (Director of US Marketing, Nan Ya CCL), Lee Ritchey (President, Speeding Edge), Scott McMorrow (CTO Signal Integrity Products, Samtec Inc.), Stephen Scearce (Hardware Engineering Manager, Cisco Systems), Amendra Koul (Technical Leader - Signal Integrity, Cisco systems inc), David Hoover (Sr Field Application Engineer - Communications & Computing Business , TTM Technologies, Inc.)

Location: Ballroom D

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 08. Optimizing High-Speed Serial Design

Format: 75-Minute Panel Discussion

Panel – Temperature and Bias Dependent Passive Component Models

Bradley Brim (Sr Staff Prod Engr, Cadence Design Systems), Istvan Novak (Senior Engineer, Oracle), Shoji Tsubota (Engineering Manager, Murata), Katsufumi EHATA (Assistant Manager, TDK Corporation), Masayuki Shimizu (Sr.Product Engineering Manager(FAE), TAIYO UDEN CO.,LTD), Tom De Muer (Keysight Technologies), Robert (Soung-Ho) Myoung (Solution Architect - CPS, ANSYS)

Location: Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: All

Format: 75-Minute Panel Discussion

Panel – Working Toward 5G: What's New From Previous Generations

Amal Ekbal (Senior Wireless Platform Architect, National Instruments), Antonio Ciccomancini Scogna (Principal Engineer, Samsung Electronics), Jose Moreira (Senior Staff Engineer, Advantest), Michael Thompson (RF Solutions Architect, Cadence), Patrick Mannion (Founder and Managing Director, ClariTek), Will Sitch (Director of Industry and Solutions Marketing, Keysight), Minnie Ho (Sr Principal Engineer and Core Technical Lead, Intel)

Location: Ballroom G

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Format: 75-Minute Panel Discussion

Thursday | 4:30 pm

Tech Trivia Quiz

Suzanne Deffree (Editor-in-Chief/Content Director, Design News, UBM)

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Audience Level: All

Format: 45-Minute Chiphead Theater Session

Thursday | 5:00 pm

Booth Bar Crawls

Location: Expo Hall

Pass Type: 2-Day Pass, All Access Pass, Boot Camp Pass, Expo Pass

Track: Happy Hour (Free)

Format: 1-Hour Networking Session

Happy Hour

Location: Expo Hall

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Happy Hour (Free)

Audience Level: All

Thursday | 5:30 pm

Passport Program Prize Announcements

Location: Chiphead Theater

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Chiphead Theater (Free)

Format: 45-Minute Chiphead Theater Session