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112G - Designer's Trade-offs and Challenges for a Successful 56/112G High-Speed SerDes Design

Saman Sadr (VP High Speed SerDes IO, Rambus)

Location: Great America 3

Date: Wednesday, January 31

Time: 10:15am - 10:55am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass - Get your pass now!

Track: Sponsored Session (Free)

Audience Level: Advanced

Format: 40-Minute Technical Session

Vault Recording: Not Recorded

Audience Level: Advanced

Rambus Inc

In the most advanced technology nodes, 10/7nm and below, all designs are becoming more difficult to implement. IP vendors face the added challenge of creating products that are usable by multiple customers, each with their own design methodology, tool flow and floorplanning issues. How to make design choices such that allow the IP to be adapted to various markets and applications. What techniques and abstractions can help IP vendors address these challenges within a reasonable design resource budget? What role does the soft IP provider play in ensuring the their designs will work well in a customers’ application? Also, as customers push harder and harder for first tapeout ramp to production for their designs, what do IP providers have to do to make this type of success more likely? How can close collaboration between Foundries, IP vendors and customers accelerate the pace of design? And most importantly how to translate such information into a decision matrix?