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112G Electrical System Performance Study based on an improved Salz SNR Methodology

Xiaoqing Dong (System engineer, Huawei Technologies)

Gongxian Jia (System Engineer , Huawei Technologies)

Vivek Shah (Engineering Director , Molex LLC)

Kingle Wang (Signal Integrity Engineer , Molex LLC)

Chunxing huang (System engineer, Shenzhen Zhongzeling Electronics)

Yu Bi (Sr. Signal Integrity Engineer , Molex LLC)

Location: Ballroom F

Date: Wednesday, January 31

Time: 10:00am - 10:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 08. Optimizing High-Speed Serial Design

Audience Level: Intermediate

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: Intermediate

In early system design stage for 112G when no silicon nor hardware components are available, an improved Salz SNR analytical model is derived and a methodology for assessing system margin is introduced. Unlike traditional ICR based Salz method, major noise terms that are recognized to be dominant and are weighted much higher in PAM4 than in NRZ systems are included. Performance 'upper limits' such as maximal tolerable insertion loss and crosstalk for 'optimal' modulation scheme is analyzed for five backplane architectures and those with higher possibility to meet the 'upper limits' are selected for full channel modeling and margin analysis.

Takeaway

An improved Salz SNR based analytical model and system margin assessing methodology is introduced for early stage system design for 112G. Performance 'upper limits' for 'optimal' modulation scheme is analyzed for studying five backplane architectures and those with higher possibility to meet the 'upper limits' are selected for margin analysis.

Intended Audience

• Basic knowledge of Salz-SNR theory
• Basic concept of PAM and partial response modulation
• Basic understanding of backplane system architectures (PCB, cable based)
• Basic concept of engineering margin for backplane system