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01. Signal & Power Integrity at the Single-Multi Die, Interposer, and Packaging Level
45-Minute Technical Session
Audience Level: All
The understanding of the power supply noise impact to the system becomes critical as the system speed increases. In this paper, PDN modeling methodology for data bus (DQ) in DDR4, Command/Address (CAC) Bus in Register DIMM, and data bus (DQ) in LPDDR4 will be provided, with/without considering DBI scheme. The impact of termination reference schemes to power noise are analyzed as well. Empirical data using a board designed for simultaneous switching noise measurement will be available to validate the effectiveness of the proposed methodology. The outlined noise differences and system tradeoffs provide practical guidelines for power distribution network noise design.
In-depth study of effectiveness of using DBI in system memory buses will be provided. Furthermore, both simulation ad measurement results with three termination schemes will be available and summarized to provide guidelines for PDN noise design.