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Behavioral FEC Models for High Speed Serial Link BER Simulation

Hsinho Wu (Design Engineer, Intel)

Mike Li (Fellow, Intel)

Masashi Shimanouchi (Design Engineer, Intel)

Location: Ballroom B

Date: Wednesday, January 31

Time: 10:00am - 10:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: Intermediate

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: Intermediate

High speed serial link technology has been pushed to send more and more information by greater distance and/or at higher data rate. Forward Error Correction (FEC) is used to improve the link performance together with the channel equalizers when they alone cannot achieve the target BER. Since behavioral high speed serial link simulation has become indispensable for the link designers, FEC effect on the link performance must be simulated too within the current simulation framework. We have developed behavioral FEC performance models for this purpose by methodically analyzing various bit error sources and FEC use scenarios.

Takeaway

Since behavioral high speed serial link simulation has become indispensable for the link designers, FEC effect on the link performance must be simulated too. Various bit error mechanisms and several types of FEC are discussed methodically developing various concepts and clarifying the relationship among them.