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Characterization and Optimization of Via Designs Using Z-parameters

Hee-Soo LEE (Lead Application Developer, Keysight Technologies)

Nathan Hirsch (PCB Engineer, Monsoon Solutions, Inc)

Orlando Bell (VP of Engineering, GigaTest Labs)

Location: Ballroom A

Date: Wednesday, January 31

Time: 11:00am - 11:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 14. Modeling and Analysis of Interconnects

Audience Level: All

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: All

With new standards such as PAM-4 or enhanced PCI-E v.5.0 and DDR5, data transfer speeds are breaking previous records and in some cases even doubling. Since the data speed gets higher and PC boards becomes more complex, vias becomes very crucial and designers need a better way to characterize and optimize vias in any high-speed channel designs. This paper proposes a Z-parameter approach that augments the traditional TDR method by providing additional insights such as frequency dependent accurate impedance read-out. Measurement data is compared to validate the Z-parameter approach for new via designs.


Understand vias and learn how to optimize them by Z-parameters. Z-parameter approach makes the via design simpler and augments the traditional TDR method by providing a frequency dependent accurate impedance read-out for vias.

Intended Audience