Use the scheduling tool below to browse all the available sessions, speakers and topics at this year's event. Find the content and sessions to fit all of your educational needs and ensure you get the most out of your time at the show.
Build your conference agenda today! By signing up for the Scheduler, you can add sessions to your "Favorites" and develop your own personalized schedule. This personalized schedule will be synced with the official DesignCon Event App.
When prototyping a technology edge SERDES (>56G line rate) for the Ethernet wireline products market, on a leading edge, deep nanometer scale silicon process, many unknowns exist which require extensive testchip and post-silicon procedures to resolve. Since de-embedding technology has its limits at these rates, state of the art package and board design are a must if good silicon visibility is desired. We describe the procedures we took when prototyping a >100Gbps line rate design and show overall silicon-to-coax channel performance reached through the application of these procedures. Our flow is based on key EM understandings and 3D simulations.
Best Known procedure and methods for the co-optimization of package-board-connector design and how to trade off between different tools that provide performance. This extends the toolset of the SI and package design engineer to the most extreme (>100GBps, > 25GHz on Rogers material PCB) interfaces in design today.
Intermediate knowledge of Signal Integrity for HSIO, PCB materials, PCB stackup and design considerations for high speed (>20GHz), 3D electromagnetic simulations, package technology, serdes front end circuits (introductory level),High frequency package and pcb measurements