• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    | Santa Clara, CA

DesignCon 2018 Schedule Builder

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Co-optimization of Silicon, package, pcb and connector footprint for optimized 100GBps PAM4 signaling

  • Stas Litski | Signal and Power Integrity Engineer, Intel
  • Itamar Levin | System Architecture Manager, Principal Engineer , Intel
Location: Ballroom B
Pass Types: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!
Track: 06. Applying PCB Design and Simulation Tools
Audience Level: Intermediate
Format: 45-Minute Technical Session
Audience Level: Intermediate
Recording: TBD

When prototyping a technology edge SERDES (>56G line rate) for the Ethernet wireline products market, on a leading edge, deep nanometer scale silicon process, many unknowns exist which require extensive testchip and post-silicon procedures to resolve. Since de-embedding technology has its limits at these rates, state of the art package and board design are a must if good silicon visibility is desired. We describe the procedures we took when prototyping a >100Gbps line rate design and show overall silicon-to-coax channel performance reached through the application of these procedures. Our flow is based on key EM understandings and 3D simulations.


Best Known procedure and methods for the co-optimization of package-board-connector design and how to trade off between different tools that provide performance. This extends the toolset of the SI and package design engineer to the most extreme (>100GBps, > 25GHz on Rogers material PCB) interfaces in design today.

Intended Audience

Intermediate knowledge of Signal Integrity for HSIO, PCB materials, PCB stackup and design considerations for high speed (>20GHz), 3D electromagnetic simulations, package technology, serdes front end circuits (introductory level),High frequency package and pcb measurements