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DC-blocking capacitors are required in almost all applications of high-speed SERDES in order to level shift the differential signal to the optimum operating point for receiver performance and to avoid DC ground loops. As we start the transition from 28G to 56G NRZ and 112G PAM4, it is crucial that the DC-blocking capacitor present a high bandwidth, near-reflectionless transition to the signal in order to maintain at least 32GHz of effective interconnect bandwidth. In this paper we discuss the steps necessary to generate a realistic, detailed capacitor model for data transmission and optimize its layout for an electrically transparent design.
The ability to generate accurate and highly tuned models is required to capture the DC blocking capacitor parasitics used in high speed channel design
Some knowledge of high-speed SERDES routing challenges preferred.