• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    | Santa Clara, CA

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Designing DC-Blocking Capacitor Transitions to Enable 56Gbps NRZ & 112Gbps PAM4

Location: Ballroom F
Pass Types: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!
Track: 08. Optimizing High-Speed Serial Design
Audience Level: Intermediate
Format: 40-Minute Technical Session
Audience Level: Intermediate
Recording: TBD

DC-blocking capacitors are required in almost all applications of high-speed SERDES in order to level shift the differential signal to the optimum operating point for receiver performance and to avoid DC ground loops. As we start the transition from 28G to 56G NRZ and 112G PAM4, it is crucial that the DC-blocking capacitor present a high bandwidth, near-reflectionless transition to the signal in order to maintain at least 32GHz of effective interconnect bandwidth. In this paper we discuss the steps necessary to generate a realistic, detailed capacitor model for data transmission and optimize its layout for an electrically transparent design.


The ability to generate accurate and highly tuned models is required to capture the DC blocking capacitor parasitics used in high speed channel design

Intended Audience

Some knowledge of high-speed SERDES routing challenges preferred.