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Effective Link Equalizations using FIR, CTLE, FFE, DFE, and FEC for Serial Links at 112 Gbps and Beyond

Hsinho Wu (Design Engineer, Intel Corp.)

Masashi Shimanouchi (Design Engineer, Intel Corp.)

Mike Peng Li (Fellow, Intel Corp.)

Location: Ballroom F

Date: Thursday, February 1

Time: 8:00am - 8:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: All

Channel equalizations (EQ) have become an essential mechanism that enables today's high-speed serial links. EQ schemes, such as TX emphasis, RX CTLE, FFE, DFE, and FEC, have being evolving with technology advances and they are deployed to compensate various channel effects. Though there are general theories with these EQ schemes, the actual usage, implementations, constraints, and most importantly, the effectiveness against various types of channel aliments among these EQ schemes are not well known or documented. In this paper, we will investigate theses EQ schemes and study their actual performance through design experiments using real world channels.


The audience will gain the knowledge on equalization mechanisms and their effectiveness/role in serial links.

Intended Audience

For audience with knowledge on high-speed serial links, jitter and noise components, and equalization schemes in serial communication links.