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Feedforward Equalizer Location Study for High Speed Serial Systems

Kevin Zheng (Research Assistant, Stanford University)

Boris Murmann (Professor, Stanford University)

Hongtao Zhang (Senior Staff Design Engineer, Xilinx Inc.)

Geoff Zheng (Distinguished Engineer , Xilinx Inc.)

Location: Ballroom C

Date: Wednesday, January 31

Time: 8:00am - 8:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 08. Optimizing High-Speed Serial Design

Audience Level: Intermediate

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: Intermediate

Data converter based SerDes are gaining increasing popularity due to their architecture flexibility and capability of implementing FFE through DSP. Conventionally, an FFE is located on the TX side due to simpler implementation of delays and gains, but it suffers from peak power constraint. On the other hand, the RX FFE isn't constrained in this fashion and its coefficients can be optimally adapted for tradeoffs between cancelling channel ISI and noise amplification. This paper provides a theoretical analysis, realistic simulations and practical comparisons between TX and RX FFE. The effects of TX DAC and RX ADC quantization are also studied.


Data converter based SerDes are attracting significant attention. Technology scaling enabled fully digital equalizers and different architectures. Specifically, feed-forward equalizer plays a crucial role and its position along the link can yield different system performance. Theoretical analysis and simulations are presented for both TX/RX FFE. Results and implications are discussed.

Intended Audience

1. Basic concept of link equalization
2. Basic idea of link system modeling
3. Statistical signal processing