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Improved Engineering Analysis in FEC System Gain for 56G PAM4 Applications

Xiaoqing Dong (System engineer, Huawei Technologies)

Geoff (Geoffrey) Zhang (Distinguished Engineer , Xilinx)

Chunxing Huang (System Engineer, Shenzhen Zhongzeling Electronics Co., Ltd.)

Location: Ballroom B

Date: Thursday, February 1

Time: 2:50pm - 3:30pm

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: Intermediate

Format: 40-Minute Technical Session

Vault Recording: TBD

Audience Level: Intermediate

In 56Gbps-PAM4 systems, it is no longer practical to rely on SerDes alone to transmit data of channels up to 30dB in loss. FEC is required to work jointly with SerDes to achieve the post-FEC BER better than a target, e.g. 1e-15.
This paper starts with the inadequate approaches adopted today for FEC capability assessment. The data based on the 28G generation KR4 FEC performance analysis and test validation is shared. A novel FEC post-processing method based on voltage bathtub curves is discussed. Recursive models for both PAM4 DFE burst error probability and KP4-FEC BER estimation are derived and presented.

Takeaway

Estimating post-FEC BER from pre-FEC BER with today method is inadequate, as different factors have different impact on FEC correction capability. This paper proposes a new concept of system gain (SG). The improved approach will arm both system and chip-design engineers with a more accurate methodology in predicting link performance.

Intended Audience

• Basic concept of link system margin and BER
• Basic idea of error correction and FEC
• Basic understanding of DFE and error propagation
• Basic knowledge of statistics and probability and statistical signal processing