• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    Center
    | Santa Clara, CA

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In-depth SI and PI analysis of chip-to-chip interconnect using silicon bridge

Location: Ballroom F
Pass Types: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!
Track: 07. Advanced IO Interface Design for Memory and 2.5D/3D/SiP Integrations
Audience Level: All
Format: 45-Minute Technical Session
Audience Level: All
Recording: TBD

A silicon process based bridge makes it possible to communicate in massive parallel IOs between memory and SoCs in a single package. Also, the silicon provides a low-impedance power delivery path between two independent power domains. However, though the length is short, the timing error in silicon bridge is not negligible due to a chip-scaled dimension inside the bridge. The silicon bridge has many un-expected sources to generate a crosstalk from adjacent signals, bump and via. Also, a switching noise in the power domain inside the bridge is another source to make an additional coupled noise to the signal routing. We investigated all noise sources inside silicon bridge and see the timing error.

Takeaway

A performance of silicon bridge between two silicon chips is investigated in terms of signal integrity and power integrity for the first time. The timing error is dominantly caused by crosstalk not only from adjacent signals but also from vertical routings and SSN coupling from the layer in the bridge

Intended Audience

SI/PI engineer working on SiP, Interposer and chip-to-chip interconnect