• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    Center
    | Santa Clara, CA

DesignCon 2018 Schedule Builder

Use the scheduling tool below to browse all the available sessions, speakers and topics at this year's event. Find the content and sessions to fit all of your educational needs and ensure you get the most out of your time at the show.

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Measuring Power Rail Noise Impact on Clock Jitter

  • Mike Schnecker (Business Development Manager, Rhode & Schwarz USA, Inc.)
Location: Great America Meeting Room 2
Pass Types: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass - Get your pass now!
Track: Sponsored Session (Free)
Audience Level: Intermediate
Format: 40-Minute Technical Session
Audience Level: Intermediate
Recording: Not Recorded

A primary contributor to timing jitter on clock signals is noise on the power plane. The primary sources of this noise are switching transients on the power supply and PDN impedance flatness. This session will cover Oscilloscope methods for evaluating noise on power rails and the relationship between this noise and jitter.