Super Early Bird Registration Now Open till October 12th. Save Up to $400 Today!

Mechanism Finding and Possible Mitigating Solutions of Serial-TX-Introduced Interference Picked Up by LC-PLL

Zhaoyin Daniel Wu (Senior Staff Engineer, Xilinx Inc)

Parag Upadhyaya (Director, SERDES Technology Group, Xilinx Inc)

Geoff Zhang (Distinguished Engineer, Xilinx Inc)

Ade Bekele (Senior Staff Design Engineer, Xilinx Inc.)

Santiago Asuncion (Product Application Engineer, Xilinx Inc.)

Yohan Frans (Senior Engineering Director, Xilinx, Inc)

Ken Chang (Vice President, SerDes Technology, Xilinx Inc.)

Location: Ballroom C

Date: Wednesday, January 31

Time: 9:00am - 9:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 01. Signal & Power Integrity at the Single-Multi Die, Interposer, and Packaging Level

Audience Level: All

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: All

Although TX to LC-PLL coupling has been confirmed not to cause an issue with on-die electromagnetic simulation, the silicon result still showed the observable TX interference impacting on total jitter. This paper will show comprehensive way to find the coupling mechanism, confirm the mechanism qualitatively and quantitatively, propose the possible solution with electromagnetic verification, and show the silicon result at the end.

Takeaway

Co-design between on-die and package, Gating of H-field, return current, silicon interposer, c4-bumps, on-die slot, slot-line isolation.

Intended Audience

Electromagnetic wave, PLL concept, microwave circuit design.