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Reduction of Mode Conversion in SerDes Links

Mehdi Mechaik (Staff Application Engineer, Cadence Design Systems)

Location: Ballroom A

Date: Wednesday, January 31

Time: 8:00am - 8:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 12. Electromagnetic Compatibility and Mitigating Interference

Audience Level: All

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: All

This paper presents a comprehensive investigation on the effectiveness and reduction of mode conversion in SerDes links for serial interface applications. It offers a technique for suppressing mode conversion caused by bend length mismatch in a differential signal pair. The technique consists of reducing trace losses, matching input and output port impedances, and minimizing deviations in differential pair characteristic impedance. Finally, numerical validation of the technique is established by extracting Scattering Parameter models using a full-wave field solver and carrying out time-domain system simulations to obtain receiver eye diagrams for a high-speed serial interface such as Peripheral Component Interface Express (PCIe) operating at 16GT/s (Gen4). This study results in characterizations and recommendations for reducing mode conversion in the lossy SerDes channel.

Takeaway

EMC engineers leave this paper discussion with new idea about controling EMC issues. They learn how mode conversion resulting from a bend in a differential pair can be reduced in a complex high-speed lossy SerDes channel if port impedances are matched and differential pair characteristic impedance does not deviate appreciably from its nominal value. They also see the technique is further validated by both scattering parameter trends and time-domain system simulations.

Intended Audience

Basic general knowledge of digital designs