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Signaling and Performance Challenges and Solutions for Next-Generation OIF CEI-112G-VSR "Chip-to-Module" Interfaces

Mike Peng Li (Fellow, Intel)

Hsinho Wu (SOC Design Engineer, Intel)

Masashi Shimanouchi (SOC Design Engineer, Intel)

Nathan Tracy (Technologist, TE)

Location: Ballroom G

Date: Wednesday, January 31

Time: 8:00am - 8:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 10. High-Speed Signal Processing, Equalization, and Coding

Audience Level: Advanced

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: Advanced

Next-generation CEI-112G-VSR "chip-to-module" interfaces (up to ~250 mm channel length and ~ 15 dB channel insertion loss (IL) at 28 GHz) are presently being specified within the Optical Internetworking Forum (OIF) in order to support development of 400G, 800G, and > 1T optical systems based upon 1 to N channel 112 Gb/s serial interfaces, with PAM4 coding. This paper will investigate host and module transmitter and receiver electrical, jitter, noise, SNDR requirements, channel topology, connector and medium, clocking and equalization, in order to meet the link performance efficiency objective.


The audience will be provided with transmitter and receiver equalization and clocking, channel topology, and medium required for PAM-4 signaling over the OIF's new 112 Gb/s VSR chip-to-module electrical interfaces including expected system performance metrics.