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Statistical-Based RE DCD Jitter Analysis in High Speed NAND Flash Memory

Sayed Mobin (Senior Manager, Western Digital)

Cindy Cui (Application Engineer , Keysight)

Location: Ballroom C

Date: Thursday, February 1

Time: 11:00am - 11:45am

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 04. System Co-Design: Modeling, simulation and measurement validation

Audience Level: All

Format: 45-Minute Technical Session

Vault Recording: TBD

Audience Level: All

Impact of RE Duty Cycle Distortion (DCD) must be integrated in NAND to Flash Management Controller (FMC) SI simulation to predict system level performance accurately in multi-die, high performance system. 50% duty cycle signal as input to NAND driver is too optimistic, while both FMC and NAND will contribute a portion of duty cycle distortion to the RE signal. This paper will focus on the importance of DCD jitter analysis at higher speed and heavier loading NAND systems, and introduce a statistical approach of DCD jitter analysis. Measurement data is provided to validate the approach.

Takeaway

The attendees will learn the importance of the RE DCD jitter analysis at higher data-rate and heavier loading NAND systems. Also, a new statistical-based NAND SI simulation methodology is demonstrated based on a real design case to show how to predict the RE DCD impact accurately and efficiently.

Intended Audience

1. Basic concept of NAND Flash system design and the specifications
2. Basic signal integrity principles such as IBIS model simulation, jitter, eye diagrams, and timing margin measurement.