• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    Center
    | Santa Clara, CA

DesignCon 2018 Schedule Builder

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Tutorial – Design & Verification for High-Speed I/Os at 10 to 112 Gbps With Jitter, Signal Integrity, and Power Optimization

Location: Ballroom C
Pass Types: All Access Pass, Alumni All Access Pass - Get your pass now!
Track: 09. Measurement, Simulation, and Optimization of Jitter, Noise, and Timing to Minimize Errors
Audience Level: All
Format: 3-Hour Tutorial
Audience Level: All
Recording: TBD

This TecForum reviews the latest design and verification developments, as well as architecture, circuit, and deep submicron process (28, 20, 14, 10 nm) technology advancements for high-speed links, with an emphasis on jitter, noise, and signal integrity for 10 -112 Gbps high-speed I/Os (e.g., GbE (10G, 40G, 100G, 400G), CEI/OIF (11G, 20-28G, 40-60G, 80-120G), Fibre Channel (16G, 32G, 64 G), and PCI Express (8G, 16G, 32G). Example studies on design and validation methods will be presented.

Takeaway

Basics knowledge on high-speed link architectures, jitter, noise, SNDR, nonlinearity, signal integrity, and related standards, design and verification methodologies, as well as the latest knowledge on the advanced topics such as 10-112 Gbps link design and verification with jitter, noise, SNDR, signal integrity, performance, and power optimization.