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Tutorial – Principles of Power Integrity for PDN Design

Larry Smith (Principal Engineer, Qualcomm)

Eric Bogatin (Signal Integrity Evangelist, Teledyne LeCroy)

Location: Ballroom B

Date: Tuesday, January 30

Time: 1:30pm - 4:30pm

Pass Type: All Access Pass, Alumni All Access Pass - Get your pass now!

Track: 11. Power Integrity in Power Distribution Networks

Audience Level: All

Format: 3-Hour Tutorial

Vault Recording: TBD

Audience Level: All

Power Quality is very important for proper CMOS circuit performance. PDN design begins by establishing DC and AC target impedances. RLC circuit elements are developed to represent the inductances and capacitances associated with the board, package and die. The PDN impedance is best managed in the frequency domain by controlling the peaks and dips. PDN noise performance in the time domain is what matters to the circuits. Time domain noise is classified into voltage responses from impulse, step and resonant current waveforms. This tutorial delivers the fundamental principles necessary for good PDN intuition.


PDN Power Integrity is important for good circuit performance. Good impedance management in the frequency domain and results in good PDN noise performance in the time domain. The voltage response to the impulse, step and resonant current waveforms are important for CMOS circuits and determine the PDN quality.