• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    | Santa Clara, CA

DesignCon 2018 Schedule Builder

Use the scheduling tool below to browse all the available sessions, speakers and topics at this year's event. Find the content and sessions to fit all of your educational needs and ensure you get the most out of your time at the show.

Build your conference agenda today! By signing up for the Scheduler, you can add sessions to your "Favorites" and develop your own personalized schedule. This personalized schedule will be synced with the official DesignCon Event App.

Tutorial – Principles of Power Integrity for PDN Design

Location: Ballroom B
Pass Types: All Access Pass, Alumni All Access Pass - Get your pass now!
Track: 11. Power Integrity in Power Distribution Networks
Audience Level: All
Format: 3-Hour Tutorial
Audience Level: All
Recording: TBD

Power Quality is very important for proper CMOS circuit performance. PDN design begins by establishing DC and AC target impedances. RLC circuit elements are developed to represent the inductances and capacitances associated with the board, package and die. The PDN impedance is best managed in the frequency domain by controlling the peaks and dips. PDN noise performance in the time domain is what matters to the circuits. Time domain noise is classified into voltage responses from impulse, step and resonant current waveforms. This tutorial delivers the fundamental principles necessary for good PDN intuition.


PDN Power Integrity is important for good circuit performance. Good impedance management in the frequency domain and results in good PDN noise performance in the time domain. The voltage response to the impulse, step and resonant current waveforms are important for CMOS circuits and determine the PDN quality.