• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    | Santa Clara, CA

DesignCon 2018 Schedule Builder

Use the scheduling tool below to browse all the available sessions, speakers and topics at this year's event. Find the content and sessions to fit all of your educational needs and ensure you get the most out of your time at the show.

Build your conference agenda today! By signing up for the Scheduler, you can add sessions to your "Favorites" and develop your own personalized schedule. This personalized schedule will be synced with the official DesignCon Event App.

Janani Chandrasekhar, SIPI Engineer , Intel

Janani Chandrasekhar is a SIPI Engineer at the Package and Platform Team at Programmable Solutions Group in Intel. Her responsibilities include core power, 2.5 EMIB and memory IO power integrity, system power delivery and chip-package-board co-design efforts. Prior to this she also has published papers on DDR4/DDR3 memory SI/PI simulation and correlation, SERDES high speed power integrity at various conferences. She holds a MS in Electrical and Computer Engineering from Georgia Institute of Technology.