Vice President, SerDes Technology,
Ken Chang (M 99, SM 14) received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1990, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, USA, in 1994 and 1999, respectively. From 1999 to 2010, he was with Rambus Inc. He led several projects including 5Gb/s/lane 12Gbytes FlexIOTM interface for CELLTM processors, 16 Gb/s and 20 Gb/s low power memory interfaces exploring various signaling techniques. Since 2010, he has been with Xilinx Inc., and led the SerDes technology group, focused on developing multi-standard SerDes IPs for FPGAs, covering top line rates from 10Gb/s, 28Gb/s, and 56Gb/s, all capable of long reach transmission. His research interests include high-speed mixed-signal CMOS circuit design, transmitter and receiver design, CDR, equalization, PLL/DLL design, circuit noise analysis, signal integrity analysis, and mixed signal design methodology.
He has authored and coauthored 40+ IEEE conference/journal publications and hold 30+ U.S. patents in the high-speed link area. He is the technical program co-chair/chair of 2017/2018 VLSI circuit symposium and had served on technical program committees for ISSCC and CICC. He is the co-author of 2008 and 2014 CICC best regular papers. He is a senior member of IEEE