• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    Center
    | Santa Clara, CA

DesignCon 2018 Schedule Builder

Use the scheduling tool below to browse all the available sessions, speakers and topics at this year's event. Find the content and sessions to fit all of your educational needs and ensure you get the most out of your time at the show.

Build your conference agenda today! By signing up for the Scheduler, you can add sessions to your "Favorites" and develop your own personalized schedule. This personalized schedule will be synced with the official DesignCon Event App.

Guang Chen, SI/PI engineer, Intel

Guang Chen is a design engineer with Silicon Systems Development Department at the Programmable Solutions Group (PSG), Intel Corporation, where he is responsible for driving signal/power integrity co-design effort for the key FPGA products with focus on both silicon and system level power integrity solutions. Prior to this, he was with Technical Service Dept. at Altera Corporation, providing system SI/PI solutions for customer Altera FPGA applications. He holds a Ph.D. in Electrical Engineering from University of Arizona. His professional interests include power integrity and signal integrity, high-speed interconnects and channel modeling.


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