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DesignCon 2019 Presentation Viewer

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Chung HuangDesign Engineering Director Cadence

Chung-Chi Huang is currently a design engineering director at Cadence primary responsible for signal/power integrity, IBIS-AMI modeling and test chip implementation for DDR IP group. Previously he was with Inphi Corporation working on LRDIMM design. He spent 10 years in Intel Corporation working on the signal integrity of high speed serial buses for XEON and Itanium family products. He received Ph.D. degree in electrical engineering from University of Washington, Seattle, in 2003.

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