• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    | Santa Clara, CA

DesignCon 2018 Schedule Builder

Use the scheduling tool below to browse all the available sessions, speakers and topics at this year's event. Find the content and sessions to fit all of your educational needs and ensure you get the most out of your time at the show.

Build your conference agenda today! By signing up for the Scheduler, you can add sessions to your "Favorites" and develop your own personalized schedule. This personalized schedule will be synced with the official DesignCon Event App.

Amiram Jibly , Senior SI Engineer, Intel

Amiram Jibly is a System Engineer in the Network ASIC design team at Intel, has been with Intel in the last 7 years and is experienced in package and board design for high speed systems and signal integrity. His current work focuses on 100 Gb Ethernet validation systems and SI. His experience includes Si/Pi simulations for 25 and 56 Gb products and accurate measurement based modeling of passive interconnects. He received his BSc Degree from the Jerusalem College of Engineering in 2012.