• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    Center
    | Santa Clara, CA

DesignCon 2018 Schedule Builder

Use the scheduling tool below to browse all the available sessions, speakers and topics at this year's event. Find the content and sessions to fit all of your educational needs and ensure you get the most out of your time at the show.

Build your conference agenda today! By signing up for the Scheduler, you can add sessions to your "Favorites" and develop your own personalized schedule. This personalized schedule will be synced with the official DesignCon Event App.

Xiaoning Ye, Principal Engineer, Intel, Corporation

Xiaoning Ye is currently a Principal Engineer at Intel Corporation, working on signal integrity of high-speed interconnects in Server systems. He received his Bachelor and Master Degrees in electronics engineering from Tsinghua University, Beijing, China, in 1995 and 1997 respectively, and the Ph.D. degree in electrical engineering from University of Missouri – Rolla (currently Missouri University of Science and Technology) in 2000. He has published over 70 IEEE and other technical papers, and holds 8 patents and a few patent applications.


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