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Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Keynote – Design for Security: The Next Frontier of Smart Silicon

Keynote: Warren Savage  (University of Maryland)

Location: Elizabeth A. Hangs Theater

Track: Keynote

Format: Keynote

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass, Boot Camp Pass, Expo Pass

Leveraging IBIS-AMI Simulations for Optimized Architectural Design in PCIe5 PHY

Speaker: Priyank Shukla  (Synopsys)

Authors: Kevin (Kai) Li  (Synopsys), Jianguo Zhou  (Synopsys), Christian de Verteuil  (Synopsys)

Location: Ballroom D

Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 07. Optimizing High-Speed Serial Design

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass

Accurate IBIS-AMI modelling of DSP-Based 56G Ethernet Transceivers & Successful Hardware to Model Correlation

Speaker: Priyank Shukla  (Synopsys)

Authors: Kevin Li  (Synopsys), Ayal Shoval  (Synopsys), Ismael Duron  (Synopsys)

Location: Ballroom B

Track: 02. Chip I/O & Power Modeling & Validation Solutions

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass

Panel – PCIe 32G & 64G: System Design & Test Challenges

Moderator: Pegah Alavi  (Keysight)

Panelists: Steve Krooswyk  (Samtec), Rita Horner  (Synopsys), Ying Li  (NVIDIA), Dan Froelich  (Tektronix), Patrick Casher  (Foxconn Interconnect Technology), David Bouse  (Tektronix), Rick Eads  (Keysight), Tim Wig  (Intel)

Location: Ballroom F

Track: 07. Optimizing High-Speed Serial Design

Format: Panel Discussion

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass, Boot Camp Pass, Expo Pass

Panel – Electronic Design Automation Roadmap for Machine Learning & AI Standardization

Moderator: John Ellis  (Silicon Integration Initiative, Inc.)

Panelists: Leigh Anne Clevenger  (Silicon Integration Initiative, Inc.), Rhett Davis  (North Carolina State University), Leon Stok  (IBM), Norman Chang  (ANSYS), Ramond Rodríguez  (Intel)

Location: Ballroom D

Format: Panel Discussion

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass, Boot Camp Pass, Expo Pass

Leigh Anne Clevenger

Title: Design Automation Data Scientist

Company: Silicon Integration Initiative, Inc.

Dr. Leigh Anne Clevenger, a professional software engineer with over 15 years' experience at IBM and GlobalFoundries, is as a Design Automation Data Scientist at Silicon Integration Initiative, Inc. (Si2), focusing on accelerating the Si2 OpenStandards Coalition collaboration efforts in machine learning and in system-level power modeling. Dr. Clevenger, who earned her doctorate in Software Engineering and Machine Learning at Pace University, has extensive experience in semiconductor design automation and semiconductor processing technology. She is a published expert in detailed circuit simulator systems, including IBM PowerSPICE, Cadence Spectre/APS/XPS/Ultrasim, and Synopsys HSPICE. At GlobalFoundries she was a software development engineer for automotive and gaming computer chips. Dr. Clevenger has published and presented research on data science, including big data analytics, machine learning algorithms, and wearable computing. She has filed over 30 patents in the areas of health care and fitness based on Internet of Things sensors, improving engagement with virtual and augmented reality and semiconductor innovations. For her doctorate, she developed a machine learning system for active screening of cardiac patients.

Ismael Duron

Title: Sr IC Test engineer

Company: Synopsys

Ismael is an Analog/Mixed-Signal and High-Speed SerDes Test engineer at Synopsys. He has more than 15 years of professional experience across different semiconductor companies working in SoC, Embedded System HW & SW teams to develop applications, IP cores and reference designs for consumer electronics, telecom, aerospace and military customers.

Horner, Rita

Title: Technical Marketing Manager, Sr. Staff

Company: Synopsys

Rita Horner is a Senior Technical Marketing Manager at Synopsys, with more than 25 years of experience in the area of mixed signal circuit design, ESD design, test and packaging of high speed integrated circuits for consumer, computing, and high end networking products, across a broad range of semiconductor process technologies. As a technical, product and strategic manager, she has worked on defining and managing ASSP, ASIC and Fiber Optic product lines, and has been focused on High Speed Serial Interconnect IPs. She participated and presented at multiple technical conferences, consortiums, and standards bodies including ANSI T11, IEEE 802.3, OIF, PCI-SIG and many Multi Souring Agreements. She has previous experience with Avago Technologies, Exar, Agilent Technologies, Hewlett-Packard and Intel. She holds an MSEE from the University of Tennessee, has a patent in IC packaging and has a number of technical publications.

Li, Kevin

Title: HW Engineer Sr

Company: Synopsys

Kevin is currently responsible for managing high speed SerDes IP SI model development and customer services that utilize SI models. He has been worked on various high speed SerDes IP SI models covering multiple protocols, with data rates ranging from 5Gbps to 32Gbps. He received both of his M.Eng in 2012, B.A.Sc in 2011, in the field of Electrical Engineering from University of Toronto. During the past 7 years, he accumulated 2-year experience as application engineer at Intel and 5-year experience in high speed SerDes IP SIPI engineering at Synopsys.

Savage, Warren

Title: Visiting Researcher, Applied Research Laboratory for Intelligence and Security

Company: University of Maryland

Warren Savage is currently a Visiting Researcher at the University of Maryland’s Applied Research Laboratory for Intelligence and Security, primarily supporting DARPA programs as a subject matter expert on a variety of research programs. He is one of the more recognized figures in Silicon Valley, having held various technical and executive roles in semiconductor, EDA, and systems companies including Fairchild, Tandem Computers, and Synopsys where he made an impact on a then nascent semiconductor intellectual property industry. He went on to found IPextreme in 2004, a semiconductor IP commercialization company, which was sold to Silvaco in 2016. Mr. Savage holds four patents, a BS in Computer Engineering from Santa Clara University and an MBA from Pepperdine University.

Ayal Shoval

Title: Sr. Member, Technical Staff

Company: Synopsys

Ayal is a system and circuit design architect leading the development of 56/112G PAM4 PHYs at Synopsys. He as over 25 years of experience in mixed-signal and high-speed SerDes development.

Shukla, Priyank

Title: Staff Applications Engineer

Company: Synopsys

Priyank is responsible for deployment of Synopsys’ High Speed SerDes IP in our customers complex SoCs. He focuses on our 56Gbps Ethernet SerDes, Multi-Protocol 16 Gbps SerDes and USB-C 3.1/DisplayPort 10Gbps SerDes IPs. His 12 years of professional career has spanned across India, APAC, and the US working for Inslico, Cadence, Analog Devices, and Applied Micro. Priyank has 7 years of Application engineering and 5 years of Analog Design experience with a US patent on low power RTC design.

Zhou, Jianguo

Title: Senior SI/PI Engineer

Company: Synopsys

Jianguo Zhou is responsible for IBIS-AMI modeling of Synopsys high speed SerDes IPs. He focuses on Multi-Protocol 32Gbps SerDes, Multi-protocol 25Gbps SerDes, Multi-protocol 16Gbps SerDes and USB-C/DisplayPort 10Gbps SerDes IPs. Jianguo has 5 years of high speed signal integrity and power integrity simulation and 2 years of high Speed SerDes IP modeling. He has spent his past 7 years of professional career at TP-LINK, ZTE and Synopsys.

de Verteuil, Christian

Title: Senior R&D Manager

Company: Synopsys

Christian leads the 32G Mulitprotocol SerDes IP post-silicon validation and characterization efforts at Synopsys. He has 19 years of experience in silicon product development and testing, with 10 years focused on high speed SerDes.