April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA


Welcome to the DesignCon 2022 agenda and presentation download site. Here you can view and download conference, Chiphead Theater, and other event presentations before, during, and after the event. If you're looking for a presentation from a specific session that you're unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalog of available presentations.

Validation of Achieving 200Gbps Signaling per Electrical Lane Over 1 Meter of Passive Twinaxial Copper Cable

Speakers: Christopher DiMinico  (MC Communications/PHY-SI LLC/SenTekse), Michael Klempa  (Amphenol ICC), David Nozadze  (Cisco Systems), Michael Rowlands  (Amphenol HSC)

Authors: Mike Resso  (Keysight Technologies), Curtis Donahue  (Rohde & Schwarz), Oj Danzy  (Keysight Technologies), Richard Mellitz  (Samtec), Mike Sapozhnikov  (Cisco Systems), Amendra Koul  (Cisco Systems), Adee Ran  (Cisco Systems), Upen Reddy Kareti  (Cisco Systems)

Location: Ballroom H

Track: 13. Modeling & Analysis of Interconnects, 12. Applying Test & Measurement Methodology

Format: Technical Session

Theme : High-speed Communications

Education Level: Introductory

Pass Type: 2-Day Pass, All Access Pass

Reflecting on Reflections: An Evaluation of New & Standardized Metrics

Speakers: Steve Krooswyk  (Samtec), Beomtaek Lee  (Intel)

Authors: Hansel Dsilva  (Achronix Semiconductor), Richard Mellitz  (Samtec), Adam Gregory  (Samtec), Stephen Hall  (Intel)

Location: Ballroom D

Track: 07. Optimizing High-Speed Link Design, 08. Measurement & Simulation Techniques for Analyzing Jitter, Noise & BER

Format: Technical Session

Theme : Data Centers, High-speed Communications

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Exploring the Requirements for 224Gbps Channel Characterization Using Simulations & Measurements

Speakers: Rick Rabinovich  (Keysight Technologies), Mike Resso  (Keysight Technologies)

Authors: Luis Boluña  (Keysight Technologies), John Calvin  (Keysight Technologies), Francesco de Paulis  (University of L'Aquila), Richard Mellitz  (Samtec)

Location: Ballroom F

Track: 07. Optimizing High-Speed Link Design, 12. Applying Test & Measurement Methodology

Format: Technical Session

Theme : High-speed Communications

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Mellitz, Richard

Title: Distinguished Engineer

Company: Samtec

Richard Mellitz is presently a Distinguished Engineer at Samtec, supporting interconnect signal integrity and industry standards. Prior to this, he was a Principal Engineer in the Platform Engineering Group at Intel. Richard was a principal member of various Intel processor and I/O bus teams including Itanium®, Pentium®, PCI Express®, SAS®, and Fabric (Ethernet, IB, and proprietary). Additionally, he has been a key contributor for the channel sections IEEE802.3 backplane and cabling standards, and for the time domain ISI and return loss standards for IEEE802.3 Ethernet, known as COM (Channel Operating Margin) and ERL (Effective Return Loss), which are now an integral part of Ethernet standards due to Rich’s leadership. He founded and chaired an IPC (Association Connecting Electronics Industries) committee delivering IPC’s first PCB loss test method. Prior to this, Rich led industry efforts at IPC to deliver the first TDR (time domain reflectometry) standard which is presently used throughout the PCB industry. Richard holds many patents in interconnect, signal integrity, design, and test. He has delivered numerous signal integrity papers at electronic industry design conferences.

Mellitz, Richard

Title: Distinguished Engineer

Company: Samtec

Richard Mellitz is presently a Distinguished Engineer at Samtec, supporting interconnect signal integrity and industry standards. Prior to this, he was a Principal Engineer in the Platform Engineering Group at Intel. Richard was a principal member of various Intel processor and I/O bus teams including Itanium®, Pentium®, PCI Express®, SAS®, and Fabric (Ethernet, IB, and proprietary). Additionally, he has been a key contributor for the channel sections IEEE802.3 backplane and cabling standards, and for the Time domain ISI analysis for IEEE802.3 Ethernet, known as COM (Channel Operating Margin), which is now an integral part of Ethernet standards due to Rich’s leadership. He founded and chaired an IPC (Association Connecting Electronics Industries) committee delivering IPC’s first PCB loss test method. Prior to this, Rich led industry efforts at IPC to deliver the first TDR (time domain reflectometry) standard which is presently used throughout the PCB industry. Richard holds many patents in interconnect, signal integrity, design, and test. He has delivered numerous signal integrity papers at electronic industry design conferences.