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100+ Gbps Ethernet Forward Error Correction (FEC) Analysis

Cathy Liu (R&D Director, OIF Board Member, Broadcom)

Location: Ballroom G

Date: Thursday, January 31

Time: 2:00pm - 2:40pm

Track: 10. High-Speed Signal Processing, Equalization & Coding, 08. Optimizing High-Speed Serial Design

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

In this study, high-speed serial link error propagation models and different Ethernet PMA/PCS schemes have been built and simulated to provide FEC performance analysis for 100/200/400GbE systems with 100+Gb/s per lane PAM4 interface. Different scenarios such as 1/(1+D) mod4 precoding, PMA bit multiplexing, symbol multiplexing and PCS RS codeword interleaving and their impacts on overall FEC performance will be discussed. Multi-part link where a single FEC shared between electrical and optical parts is studied as well. Advanced FEC schemes over current KP4 code will be explored at the end.


This study will provide comprehensive analysis for FEC performance for next generation 100Gb/s per lane 100/200/400GbE system.

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