April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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224Gbps-PAM4 End-to-end Channel Solutions for High-density Networking System


Jenny Jiang  (Principal Engineer, Intel)


Mike Li  (Intel Fellow, Intel)

Ed Milligan  (Sr. Director, Intel)

John Medina  (Design Engineer, Intel)

Qian Ding  (Design Engineer, Intel)

Kemal Aygun  (Sr. Principal Engineer, Intel)

Hsinho Wu  (Design Engineer, Intel)

Masashi Shimanouchi  (Design Engineer, Intel)

Yee Lun Ong  (Signal Integrity Design Lead, Intel)

Stas Litski  (Team Leader of the Signal and Power Integrity, Intel)

Sandeep Mada  (Analog Engineer, Intel)

Location: Ballroom H

Date: Thursday, April 7

Time: 2:00 pm - 2:45 pm

Track: 07. Optimizing High-Speed Link Design, 06. System Co-Design: Modeling, Simulation & Measurement Validation

Format: Technical Session

Theme : High-speed Communications

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: All

In this paper, the signal integrity design challenges in the 224Gbps-PAM4 networking system are analyzed, and the key enablement solutions are proposed. These challenges include how to breakdown the link budget among system components of package, board, cable, and connectors, and how to design these components to meet their respective budgets. Package design needs to consider higher-order mode propagation and dispersion, plane resonance, transmission loss, cross talk, vertical transition, and BGA ball pitch and ball pattern. PCB design requires a careful pin field area trace breakout and via optimization to address the via-to-via and trace-to-via coupling, especially in the small ball pitch high-density switch board design. Moving to 224Gbps-PAM4 from 112Gbps-PAM4, cable and connector may become gating factor due to the limitation of backward compatibility, innovation design of cable and connector will give more margin to the system. Amongst all these challenges, transmission loss is the biggest one. In this paper, we proposed feasible/realizable loss budget for package, board, cable, and connector for a high-density switching system with up to 512 lanes operating at 224Gbps-PAM4 data rate per lane, and a total end-to-end loss (bump-to-bump) budget <= 40dB at Nyquist frequency. Associated package and board enablement solutions are proposed.


The proposed system loss breakdown and technology enablement will lead to a successful 224Gbps-PAM4 high-density network system design. A <0.8mm BGA ball pitch and <1mm core thickness is essential for package functionality, a skip-layer configuration can efficiently reduce the transmission loss. An innovative via configuration can help reduce the PCB trace-to-via and via-to-via coupling.