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32-Gbps Channel Design for High Volume Platform Applications

Mohiuddin Mazumder (Principal Engineer, Intel Corporation)

Anupriya Sriramulu (Hardware Engineer, Intel Corporation)

Prerana Singaraju (Hardware Engineer, Intel Corporation)

Raul Enriquez (Technical Lead, Signal Integrity , Intel Corporation)

Alaa Ali (Signal Integrity Engineer, Intel Corporation)

Dan Froelich (Principal Engineer, Intel Corporation)

Location: Ballroom C

Date: Thursday, January 31

Time: 11:00am - 11:45am

Track: 14. Modeling & Analysis of Interconnects, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

In this paper, we describe a statistical analysis methodology coupled with PCIe channel compliance simulation method to assess the impact of one or more channel components on the channel solution space at 32 Gb/s. We provide quantitative measures of necessary improvements in S-parameters related to loss, reflection, and crosstalk. We apply our proposed methodology to assess the impact of manufacturing and design variations. Our simulations show that a PCB via stub length reduction of ~15 mils and ~1 dB package reflection reduction can make 35% failing cases pass highlighting the need for co-optimization of Si, package, and platform.


The design of 32 Gb/s channels for high-volume platforms requires extreme co-optimization of Si, package, and platform components from architectural phase. As little as 1 dB package reflection increase and 15 mils of board via stub length increase can reduce the platform channel solution space by more than 25%.

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