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DesignCon 2020 Schedule Builder
Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
400G BER and Jitter Tolerance Test for 53Gbaud PAM4 with FEC
Hiroshi Goto (Business Development Manager, Anritsu)
Location: Great America 2
Date: Thursday, January 30
Time: 2:50pm - 3:30pm
Track:
Sponsored Session
Vault Recording: TBD
As a follow-up to afternoon session “400G PAM4 BER Test Solution (IEEE802.3, CEI, IBTA)”, Anritsu will conduct a live demo of PAM4 BER test. 32Gbaud PAM4 BERT test and jitter/noise tolerance test capability of 53Gbps PAM4 data signals will be demonstrated. In addition, 128Gbps generation using new PAM4 Pulse Pattern Generator (PPG) will be introduced.
