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6.4Gb/s Single-Ended Transceiver Techniques for DDR5 Server Applications

Tingting Pang (Signal/Power Integrity (SI/PI) Engineer, Huawei Technologies)

Tianyu Liang (Signal/Power Integrity (SI/PI) Engineer, Huawei Technologies)

Zhihua Xu (Signal/Power Integrity (SI/PI) Engineer, Huawei Technologies)

Gang Zhao (Principal Engineer, Huawei)

Location: Ballroom B

Date: Thursday, January 31

Time: 8:00am - 8:45am

Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 10. High-Speed Signal Processing, Equalization & Coding

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

For explosively increasing demand of higher speed, bandwidth and density in server application, the single-ended DDR5 I/O operation frequency will be driven to be 6.4Gb/s in future. Since DDR5-SDRAM still employs multi-drops and parallel single-ended architecture to signaling, channel issues deteriorated in higher data-rate, such as inter-symbol interference (ISI) and crosstalk, will be the major barrier for 6.4Gb/s application. Besides, DDR5-SDRAM uses the un-matched DQS-DQ path like LP-DDR4 to maintain the speed increase, which is incapable to track correlated power supply induced jitter (PSIJ) between data and strobe. Therefore, the amplified jitter effect hurts timing margin. To make the 6.4Gb/s application happen, this paper analyzes the DDR5 transceiver requirements including a combination of equalization techniques and power distribution network (PDN) design, based on multiple realistic channel topologies.


For 6.4Gb/s server application, DDR5 transceiver requires a combination of equalization techniques aiming at ISI and crosstalk issues, and it also needs an optimal PDN design to minimize the PSIJ effect.

Intended Audience

The audience should have a basic knowledge of DDR architecture and transceiver design, and they also need to understand signal and power integrity.

Presentation Files