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A C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits

Makoto Nagata (Professor, Kobe University)

Norman Chang (Chief Technologist, Ansys)

Akihiro Tsukioka (Student, Kobe Uni)

Karthik Srinivasan (Senior Product Manager, Ansys)

Location: Ballroom F

Date: Wednesday, January 29

Time: 9:00am - 9:45am

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 10. Power Integrity in Power Distribution Networks

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Cryptographic algorithms are vulnerable to implementation attacks on side-channel (SC) leakage information. This paper introduces an efficient simulation technique of SC leakage at the full IC chip level. Tool chains and modeling flows will be explained in detail. The whole power delivery network (PDN) including Si substrate is captured in a chip power model (CPM) and then integrated in a chip-package-system board (CPS) model. The proposed technique was demonstrated with an advanced encryption standard (AES) Si test chip for SC leakage evaluation using correlation power analysis (CPA) over 1000 different plain texts through power delivery and Si substrate combined networks.

Takeaway

Understanding of side-channel passive attacks on cryptographic devices through simulation of AES silicon chip examples. An efficient chip-package-system board (C-P-S) simulation technique will be experienced with established flows to derive full-chip level chip power model (CPM) using commercially available tool chains. The correlation with measurements will be also exemplified.