DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!

DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

A Comparative Study of Equalization Schemes for 112G PAM4 Links

Yuchun Lu (Principle Engineer, Huawei Technologies)

Davide Tonietto (Director of SerDes Development, Huawei Canada)

Henry Wong (Distinguished Engineer, Huawei)

Weiyu Wang (Senior Engineer, Huawei)

Pengchao Zhao (Senior Engineer, Huawei)

Location: Ballroom C

Date: Wednesday, January 30

Time: 9:00am - 9:45am

Track: 10. High-Speed Signal Processing, Equalization & Coding, 08. Optimizing High-Speed Serial Design

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Trade-off between Analog front end (AFE) and analog-to-digital (ADC) designs, DSP equalization schemes and stronger FEC should be considered throughout in high speed electrical design to overcome the technical challenges at rates of 112Gbps and beyond. This work makes a comparative study of these factors with IEEE 802.3ck channels. Advanced equalization schemes and stronger FEC can ease the requirement on analog front end (AFE) and analog-to-digital (ADC) designs and extend the design space of 112G links in order to enhance the performance or reduce the overall chip area and power.


Advanced equalization schemes and stronger FEC can ease the pressure of analog front end (AFE) and analog-to-digital (ADC) designs, it provides another dimension of design to reduce the over-all complexity and power consumption. DSP configurations, CTLE bandwidth, ADC resolution as well as baud rate will be explored.

Intended Audience

Hands-on knowledge of SerDes and FEC. Familiarity with channel parameters such as crosstalk and insertion loss and SNR. Basic understanding of ADC and CTLE.

Presentation Files