April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Speaker:
Kinger Cai (Platform Electrical Architect, Intel)
Authors:
Jayanth Kalyan (Analog Engineer, Intel)
Vishram Pandit (Principal Engineer, Intel)
Ashwini Anil Kumar (Analog Engineer, Intel)
Andrea Astua Moya (Analog Engineer, Intel)
Location: Ballroom D
Date: Wednesday, April 6
Time: 3:00 pm - 3:45 pm
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 10. Power Integrity in Power Distribution Networks
Format: Technical Session
Theme : Consumer Electronics
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
As we are shrinking the process node and reducing nominal voltages, voltage margins available at the transistors are shrinking. Higher IO data rate requirements with each new generation is exacerbating the system design. Modern systems are looking for all day battery life on laptops and tablets, while some systems needs to be optimized for cost. This paper compares the voltage regulator implemented on mother board against a fully integrated voltage regulator on silicon and identifies the scenario when one can be chosen over the other. Lab data for both the implementations will also be shared.
Voltage Margins are squeezed with increased data rates and lower voltage. Based on the system, cost and power and performance requirements, designer has to choose between using an Discrete Voltage Regulator on board or a Fully Integrated Voltage Regulator on die
Knowledge about power integrity, power electronics, voltage regulator, system design, packaging, PCB design, power and performance metrics