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A Methodology for Performance Comparison of Center & Edge Sampling in Serial Links

David Cassan (Technical Director, Huawei Canada)

Hossein Shakiba (Principal Design Engineer, Huawei Canada)

Behzad Dehlaghi (Senior Analog IC/System Design Engineer, Huawei Canada)

Shayan Shahramian (Senior Analog IC/System Design Engineer, Huawei Canada)

Davide Tonietto (Director of SerDes Development, Huawei Canada)

Location: Ballroom A

Date: Thursday, January 31

Time: 11:00am - 11:45am

Track: 08. Optimizing High-Speed Serial Design, 10. High-Speed Signal Processing, Equalization & Coding

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

For the next generation of high-speed links, edge sampling can be considered as an alternative to center sampling to relax the bandwidth requirements. This paper presents a methodology to model the system and evaluate the performance for both center and edge sampling. Statistical eye analysis is used to determine the performance of the system. Using a cycle accurate bit-true time-domain model clock recovery loop dynamics and timing impairments are captured. The final statistical eye captures both voltage and timing impairments to better evaluate the system performance. The performance cross-over point between center and edge sampling under different conditions is presented.


A methodology is proposed to accurately model and compare the performance of center and edge sampling systems. Although center sampling has provided the optimal solution for existing serial links, edge sampling needs to be revisited as data rates increase. Using statistical and time-domain models, a performance cross-over point is determined.

Intended Audience

Familiarity with wireline transceivers (equalization and clock and data recovery). Basic understanding of random variables and probability. Basic understanding of partial response signaling theory.

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