April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA


Welcome to the DesignCon 2022 agenda and presentation download site. Here you can view and download conference, Chiphead Theater, and other event presentations before, during, and after the event. If you're looking for a presentation from a specific session that you're unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalog of available presentations.

A New Challenge for Neuromorphic Computing Systems: From Off-chip Interconnects to On-chip Interconnects

Speakers:

Taein Shin  (Graduate Student (PhD), KAIST)

Seongguk Kim  (Ph.D. Candidate, Korea Advanced Institute of Science and Technology)

Joungho Kim  (Professor, KAIST)

Authors:

Hyunwook Park  (Graduate Student (PhD), KAIST)

Keunwoo Kim  (Graduate Student (PhD), KAIST)

Keeyoung Son  (Graduate Student (PhD), KAIST)

Location: Ballroom D

Date: Wednesday, April 6

Time: 8:00 am - 8:45 am

Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Format: Technical Session

Theme : Consumer Electronics, High-speed Communications

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: All

Parallel matrix operation for AI consumes an enormous amount of computing energy because it requires lots of off-chip memory access. Therefore, it is an important challenge that is the minimization of off-chip memory access. A neuromorphic system is a full changed computing architecture from off-chip interconnects to on-chip interconnects by integration of computation into the memory using non-volatile resistive memory within one core.
In this paper, we modeled and analyzed a non-volatile resistive memory-based neuromorphic system as a future computing architecture for neural network processing. We focused on interconnects to verify the applying possibility of interconnects and effects on the system. For understanding the actual effect on operation, the regression of deep neural network (DNN) was demonstrated in the co-modeled neuromorphic system using ReRAM based crossbar array. With on-chip interconnect dimensions in DNN operation, the accuracy of the DNN was affected by the interconnects such as IR drop, crosstalk, or RC delay and the non-linearity of ReRAM according to the input voltage level. The effects according to the interconnects dimension and operating frequency were clearly confirmed. Finally, it was demonstrated that the accuracy and power consumption according to the array configuration for an efficient neuromorphic system.

Takeaway

We modeled and analyzed a non-volatile resistive memory based neuromorphic system for neural network processing focusing on interconnects. With on-chip interconnect dimensions in DNN operation, it is demonstrated that the accuracy and power consumption according to the array configuration for an efficient neuromorphic system, as a future computing architecture.