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A Novel Design Methodology That Solves Todays System-Level Analysis Challenges

Jim Godwin (EDA Engineer, Texas Instruments)

Chanakya K V (Lead EDA Engineer, Texas Instruments)

RItabrata Bhattacharya (Principal Engineer, Product, Cadence Design Systems)

Taranjit Kukal (Sr Product Engineering Architect, Cadence Design Systems)

Location: Ballroom E

Date: Thursday, January 30

Time: 11:00am - 11:45am

Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Typical analog design verification systems do not include test environments in simulation, leading to greater possibilities of device failure. There is an immediate need for a system where device (DUT), HIB (Hardware Interface Board) and ATE (Automatic Test Equipment) could be simulated in a familiar design environment seamlessly. This paper proposes the methodology to bring the HIB components and connectivity to design environment and perform top level system verification of HIB and DUT together before an ATE hardware tape out. Citing two practical use cases, key benefits include overall reduction in test hardware development cycle and flexibility between choosing only a functional verification and a full custom sanity.

Takeaway

Methodology to bring the HIB components and connectivity to pre-silicon design environment; Top level system verification of HIB and DUT together before an ATE hardware tape out.