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A Novel Platform PI Isolation Design Approach, Upon IFPI with SPIM & UPIT

Kinger Cai (Manager Engineering, Intel Corp.)

Location: Ballroom C

Date: Thursday, January 31

Time: 2:00pm - 2:40pm

Track: 11. Power Integrity in Power Distribution Networks, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Platform power integrity design, has been facing the challenges of neither having effective EDA tool, nor unified PI model & target, to address platform design differentiation. Conventionally platform customers had no other choice but to rigidly follow the single point PI solution, or "copy exactly" from customer reference board. In this paper, a novel platform power integration isolation design approach has been developed, based upon IFPI (Intel Fast Power Integrity) architecture with SPIM (Standard PI model) and UPIT (Unified PI Target), to efficiently address customers' platform design innovation for merged PDN (power delivery network) design, review and sign off.


For one client product supports 10+ stack-ups, with options of components stuffing and sockets, in order to support customers' High-Volume-Manufacture (HVM) largely platforms design differentiation and innovation, besides providing conventional platform design guideline with one set of PD BOM as a starting baseline PI solution, scalable platform PI design approach iFPI has been successfully integrated into commercial EDA tools, and deployed to both internal and external customers with SPIM and scalable UPIT, to enable platform PI design flexibility with trade-off among available MLCC, form-factors, cost and performance, to facilitate platform PI design review and sing-off efficiently, to reduce customer support effort, while enabling out-of-guideline designs.

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