DesignCon 2022 Schedule Builder

As the performance of the GPU continues to increase, system performance is limited by DRAM bandwidth provided by interconnection. Also, interconnect energy during the data movement is the critical limitation to scale system performance. In this paper, we propose a processing-in-memory of high bandwidth memory (PIM-HBM) scheme including system architecture and hardware structure. The proposed scheme embeds processing units into a logic layer of the HBM to reduce the cost of interconnection. To expose excess DRAM bandwidth, the DRAM architecture is reorganized and the data rate of the TSV channel is increased. Also, the total energy consumption is decreased by capacitance-reduced channel structure. We designed the overall architecture and structure with physical feasibility. The logic layer and DRAM layer for DRAM bandwidth extension are designed. Also, all interconnect channels in the proposed PIM-HBM are designed and analyzed considering SI and energy consumption. Based on the physical design, we obtained the detailed interconnect length. We modeled the energy and delay of the channels through SPICE simulation. To analyze the impact of interconnect channels on system performance and efficiency, cycle-accurate simulation is conducted. As a result, the proposed PIM-HBM outperformed the conventional GPU-HBM in terms of computing performance and energy efficiency.

Takeaway

We propose a processing-in-memory of high bandwidth memory (PIM-HBM) scheme to reduce the cost of interconnection: DRAM bandwidth and interconnect energy. With a circuit and system simulation, the impact of interconnect channels on system performance are evaluated. The proposed PIM-HBM outperformed the GPU-HBM according to computing performance and energy efficiency.