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Dmitry Klokotov (Staff Signal Integrity Engineer, Xilinx)
Location: Ballroom G
Date: Wednesday, January 29
Time: 12:00 pm - 12:45 pm
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 10. Power Integrity in Power Distribution Networks
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
This work presents a system-level study of power supply noise coupling between different power distribution networks. Our system is built around a large programmable SoC device. Such devices are used in a variety of cutting-edge applications: AI, Cloud, IoT, etc. An SoC chip hosts many different blocks with different power demands, restrictions, and requirements. Different blocks need to operate side by side and interact with each other. Insuring power integrity of such a system becomes challenging. It is particularly difficult to manage noise coupling via shared return path. Our power integrity study covers pre-silicon modeling, hardware verification, and correlation steps.
We presented a system-level power integrity study of a large SoC device. The primary focus was voltage noise coupling between independent power distribution networks. The coupling mechanism in that case is via shared ground. ANSYS CPM model flow was used to capture die-level coupling. Simulation results were verified through measurement.