April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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A T-coil Enhanced 18Gbps Memory Interface with Tx Bandwidth Extension & Rx Training Technique


Billy Koo  (Principal engineer, Samsung Electronics)

Location: Ballroom E

Date: Thursday, April 7

Time: 3:00 pm - 3:45 pm

Track: 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations, 06. System Co-Design: Modeling, Simulation & Measurement Validation

Format: Technical Session

Theme : Autonomous

Education Level: All

Pass Type: 2-Day Pass, All Access Pass

Vault Recording: TBD

Audience Level: All

A high-speed memory interface achieving 18Gb/s/pin on 8nm FinFET process has been presented. A thin-oxide high-voltage output driver with level-shifting pre-driver is developed and dual-mode equalization in Tx is proposed to compensate for both ISI and FEXT. A simultaneous calibration of clock pahse and reference voltage is proposed in Rx for high accuracy and reduced search time. A multi-phase gate training is proposed to create an internal source synchronous clock with finite cycles, thus reduce power consumption of Rx FIFO with minimum latency. Also T-coil base bandwidth extension techniques enhanced memory READ/WRITE performance up to 18Gbps.


T-coil base bandwidth extension technique for bi-directional memory interface can be achieve power efficiency improvement with small area consumption. This research will be the guideline for designing high-speed parallel memory interface for next generation.