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Accelerate Interposer Design Efficiency Using Neural Networks & Genetic Algorithms

Xiao-Ming Gao  (Engineer, Intel Corporation)

Naveid Rahmatullah  (Manager, Intel)

Taylor Hogan  (Senior Software Architect , Cadence)

Jorge Gonzalez  (Software Engineer II, Cadence Design Systems)

Location: Ballroom D

Date: Thursday, January 30

Time: 12:00 pm - 12:45 pm

Track: 14. Machine Learning for Microelectronics, Signaling & System Design

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

Most EDA tools on the market today are not able to deal with complex SoC interposer layout due to stringent routing constraints, rapid changing technology, and irregular routing patterns. Therefore, the routing has to be done manually to achieve satisfactory results. To address this challenge, we propose a new approach based on machine learning that utilizes advanced neural networks and genetic algorithms to leverage the parallel processing power of modern computing hardware. The process uses a heuristic approach to find the optimal solutions to new problems by learning from past designs and drastically reduces the layout time and resources.


Machine learning-based smart router can accelerate PCB layout process efficiency and drastically reduce routing time and resources.

Presentation File