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Location: Ballroom B
Date: Wednesday, January 29
Time: 12:00pm - 12:45pm
Track: 02. Chip I/O & Power Modeling & Validation Solutions
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: Intermediate
56Gbps/112Gbps PAM-4 PHYs are becoming the default technology for up to 800G network solutions in order to meet architectural requirements such as power, number of lanes, cost/performance. To accommodate such high data rates, most of the available PHYs on the market have moved from PVT highly dependent and hard to scale analog architectures to more robust and flexible DSP implementations. This architectural shift has implications on simulation and modelling, which has traditionally been handled by IBIS-AMI models. This paper will highlight key concepts for accurate IBIS-AMI model generation and simulation of DSP-based transceivers, and demonstrate the modelling performance through silicon correlation.
Attendee will learn about:
• The basic IBIS-AMI modelling concepts with a PAM-4 56Gbps Ethernet transceiver
• differences between analog vs DSP receiver, highlighting the current modelling considerations and key improvement needed for a reliable IBIS-AMI model
• Modelling Accuracy demonstrated through test-chip hardware correlation