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Xiaoping Liu (Senior Analog Engineer, Intel Corporation)
Wendem Beyene (SI/PI Manager, Intel Corporation)
Location: Ballroom B
Date: Thursday, January 30
Time: 9:00am - 9:45am
Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: Intermediate
In this paper, a comprehensive and accurate PSIJ pre-silicon simulation methodology for high-speed SERDES is developed and correlated with lab measurements. Accurate frequency-dependent distributed on-chip PDN models are extracted with ports defined near the transistors. The simulated system-level supply noise profiles are inputted to the system model of the transceiver block to generate the PSIJ data. The jitters of victim lane are measured with and without the extreme power state transitions of the aggressor lanes. Hence, the victim lane's PSIJ data caused by the PDN noise coupling from the aggressor lanes in various operating scenarios are successfully correlated with simulations.
For high-speed SERDES, an accurate comprehensive methodology of PSIJ simulation is developed and good correlations with lab measurements are achieved. An accurate on-chip model extraction method is adopted and noise simulations for most complicated power transitions are performed. The PSIJ and coupled noise are correlated for SERDES operating at tens-of-Gbps.
Some familiarity of high-speed transceiver designs including power supply impedance modeling, noise, and jitter analysis.