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Achieving a Robust Power Integrity Solution While Integrating Multiple IPs

Praveen Pai  (Analog Engineer, Intel)

Vishram Pandit  (Technical Lead (Signal/Power Integrity), Intel)

Location: Ballroom B

Date: Wednesday, January 29

Time: 9:00am - 9:45am

Track: 10. Power Integrity in Power Distribution Networks

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

During product design phase, IP integration effort takes place very first to define the die floor plan and then this floor structure will be used for packaging/mother board design. Later when we use the identified floor plan we sometimes do not meet the coupling level requirement with all possible package/board enablers. One reason being the adjacent IP being noisy source located next to a sensitive IP in the floor plan. In this scenario package/mother board layout could only offer limited noise isolation. We propose a scheme during IP integration for optimized floor plan for lowest coupling noise to begin with.


Today the problem is even with all enablers we use to achieve best possible layout isolation through the package till the mother board, the coupling levels achieved sometimes do not meet the requirement. The learning here was that package/mother board layout can offer isolation to certain levels, for further coupling reduction the IP floor plan was a key enabler.

Presentation File