April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA

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Addressing 112G Connector+PCB Modeling Without Having to Simulate with Terabyte Servers


Davi Correia  ( Sr Principal Application Engineer, Cadence)

Michael Rowlands  ( SI Engineering Manager, Amphenol HSC)

Location: Mission City Ballroom B5

Date: Thursday, April 7

Time: 12:00 pm - 12:45 pm

Track: Sponsored Session

Format: Sponsored Session

Education Level: All

Pass Type: 2-Day Pass, All Access Pass, Expo Pass

Vault Recording: TBD

Audience Level: All

As signaling speeds increase to 112 Gbps and beyond, it becomes essential to model the PCB and the connector as a single structure. Traditionally, this has been a daunting task that requires large servers with over 100 cores and terabytes of RAM. And even with this kind of compute power, simulations can run for days. To meet tight schedules, engineers require the ability to design, simulate, find a problem, fix a problem, and re-simulate. Ideally, they are empowered to run through this cycle multiple times per day.