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Addressing PCIe Gen5 Test and Debug Challenges with Confidence

Dan Froelich (Domain Expert – PCIe, Tektronix)

Location: Mission City M1

Date: Thursday, January 31

Time: 11:05am - 11:45am

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD


Due to increasing requirements imposed by cloud-based computing, storage capacity, and network bandwidth, the server/storage industry is rapidly progressing from PCIe Gen3 to PCIe Gen4 to PCIe Gen5. This rapid progression brings an entirely new set of test and measurement challenges for both base silicon testing and CEM compliance testing. This session will discuss these new test and measurement challenges for PCIE Gen 5 and provide insights on how new test solutions can assist with automation, validation, and debug.