April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
Advanced Testing Challenges at 32GBaud PAM4 with PCIe 6.0
Speakers:
Rick Eads (Principal Program Manager for Serial Computer Bus Technologies, Keysight Technologies)
Pegah Alavi (Senior Applications Engineer at Keysight Technologies focused on Signal Integrity and High Speed Digital Systems and Applications, Keysight Technologies)
Location: Mission City Ballroom B4
Date: Thursday, April 7
Time: 8:00 am - 8:40 am
Track: Sponsored Session
Format: Sponsored Session
Education Level: All
Pass Type: 2-Day Pass, All Access Pass, Expo Pass
Vault Recording: TBD
Audience Level: All
PCI Express 6.0 doubles Gen5’s data rate achieving a maximum data throughput of 64GT/s. It does this without needing to increase the bandwidth of the Gen5 channel by utilizing PAM4, multi-level signaling which allows PCIe 6.0 to transmits two data bits per symbol. Nevertheless, PAM4 ushers new challenges in testing at the physical layer and new measurements will need to be made to PCIe Gen6 silicon such as SNDR and multi-edge jitter. This session will help you better understand some of the key challenges of moving from NRZ (non-return-to-zero) to PAM4 technology along with new measurement requirements for transmitter and receiver testing. This seminar leverages test data from Keysight’s pathfinding efforts supporting the development of PCIe Express 6.0 technology along with similar signaling approaches used in the IEEE 802.3 and CEI 4.0 standards.
Takeaway
1. NRZ vs. PAM4 signaling differences
2. SNDR: challenges associated with measuring noise
3. TX and RX Measurement methods with PAM4 signals
