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AI Interposer Power Modeling & HBM Power Noise Prediction Studies

Jinsong Hu (Principal Application Engineer, Cadence)

Yongsong He (Staff Engineer , Enflame Tech)

Location: Ballroom A

Date: Wednesday, January 29

Time: 2:50pm - 3:30pm

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

With AI and machine learning rapidly growing in recent days, HBM technology with much higher memory bandwidth is required for parallel computation applications. For AI chip designers, they are facing much more challenges in high power consumption, high density, limited space, high signal quality and power noise performance etc.
This paper firstly discusses one large-scale AI interposer design and its modeling techniques. Then the extracted models are used in the system-level HBM simulation, several new methodologies are implemented to predict the critical power noise. Finally, the simulated signal and power performance correlates well with the HBM vendor's reference data.

Takeaway

This paper discusses one large-scale AI interposer design and its power modeling techniques, also proposes two innovative methodologies to predict HBM system power noise.

Intended Audience

SI/PI/high-speed design experience, silicon interposer design experience